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<title>linux.git/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c, branch dev</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<id>http://git.gnuabordo.com.br/linux.git/atom?h=dev</id>
<link rel='self' href='http://git.gnuabordo.com.br/linux.git/atom?h=dev'/>
<link rel='alternate' type='text/html' href='http://git.gnuabordo.com.br/linux.git/'/>
<updated>2018-08-27T16:10:47+00:00</updated>
<entry>
<title>drm/amdgpu: remove the queue manager</title>
<updated>2018-08-27T16:10:47+00:00</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-07-16T13:19:20+00:00</published>
<link rel='alternate' type='text/html' href='http://git.gnuabordo.com.br/linux.git/commit/?id=869a53d4d7d7976d039b9389aa90b6f3d29ed234'/>
<id>urn:sha1:869a53d4d7d7976d039b9389aa90b6f3d29ed234</id>
<content type='text'>
Not needed any more since that is now done by the scheduler.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: implement harvesting support for UVD 7.2 (v3)</title>
<updated>2018-07-27T14:07:44+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2018-07-25T20:11:34+00:00</published>
<link rel='alternate' type='text/html' href='http://git.gnuabordo.com.br/linux.git/commit/?id=f1e582ebfd703ea01dc4caf4d339b7c84ec3ff29'/>
<id>urn:sha1:f1e582ebfd703ea01dc4caf4d339b7c84ec3ff29</id>
<content type='text'>
Properly handle cases where one or more instance of the IP
block may be harvested.

v2: make sure ip_num_rings is initialized amdgpu_queue_mgr.c
v3: rebase on Christian's UVD changes, drop unused var

Reviewed-by: James Zhu &lt;James.Zhu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: expose only the first UVD instance for now</title>
<updated>2018-07-25T20:05:32+00:00</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-07-18T12:17:59+00:00</published>
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<id>urn:sha1:4d4831a3dae3161ab5a96694462eff708dfefc71</id>
<content type='text'>
Going to completely rework the context to ring mapping with Nayan's GSoC
work, but for now just stopping to expose the second UVD instance should
do it.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add AMDGPU_HW_IP_VCN_JPEG to queue mgr</title>
<updated>2018-06-15T17:20:40+00:00</updated>
<author>
<name>Boyuan Zhang</name>
<email>boyuan.zhang@amd.com</email>
</author>
<published>2018-05-01T18:59:12+00:00</published>
<link rel='alternate' type='text/html' href='http://git.gnuabordo.com.br/linux.git/commit/?id=b7e6cd57027f5151d4f330dfabb0182f78d26e83'/>
<id>urn:sha1:b7e6cd57027f5151d4f330dfabb0182f78d26e83</id>
<content type='text'>
Add AMDGPU_HW_IP_VCN_JPEG to queue mgr

Signed-off-by: Boyuan Zhang &lt;boyuan.zhang@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/vg20:Enable 2nd instance queue maping for uvd 7.2</title>
<updated>2018-05-18T21:08:14+00:00</updated>
<author>
<name>James Zhu</name>
<email>James.Zhu@amd.com</email>
</author>
<published>2018-04-24T01:00:58+00:00</published>
<link rel='alternate' type='text/html' href='http://git.gnuabordo.com.br/linux.git/commit/?id=04305acb9f7fc9978ed7a14bf965802c45ea9682'/>
<id>urn:sha1:04305acb9f7fc9978ed7a14bf965802c45ea9682</id>
<content type='text'>
Enable 2nd instance uvd queue maping for uvd 7.2. For user, only one UVD
instance presents. there is two rings for uvd decode, and
4 rings for uvd encode.

Signed-off-by: James Zhu &lt;James.Zhu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/vg20:Restruct uvd to support multiple uvds</title>
<updated>2018-05-18T21:08:12+00:00</updated>
<author>
<name>James Zhu</name>
<email>James.Zhu@amd.com</email>
</author>
<published>2018-05-15T19:25:46+00:00</published>
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<id>urn:sha1:2bb795f5ba9cd676536858a978b9df06f473af88</id>
<content type='text'>
Vega20 has dual-UVD. Need Restruct amdgpu_device::uvd to support
multiple uvds. There are no any logical changes here.

Signed-off-by: James Zhu &lt;James.Zhu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Downgrade DRM_ERROR to DRM_DEBUG in amdgpu_queue_mgr_map</title>
<updated>2017-12-06T17:48:06+00:00</updated>
<author>
<name>Michel Dänzer</name>
<email>michel.daenzer@amd.com</email>
</author>
<published>2017-11-22T14:55:21+00:00</published>
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<id>urn:sha1:43fbcde020f100c86fb54cbb2610164466dc8b0e</id>
<content type='text'>
Prevent buggy userspace from spamming dmesg.

Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Michel Dänzer &lt;michel.daenzer@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Use unsigned ring indices in amdgpu_queue_mgr_map</title>
<updated>2017-11-28T22:44:14+00:00</updated>
<author>
<name>Michel Dänzer</name>
<email>michel.daenzer@amd.com</email>
</author>
<published>2017-11-22T14:55:21+00:00</published>
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<id>urn:sha1:fa7c7939b4bf112cd06ba166b739244077898990</id>
<content type='text'>
This matches the corresponding UAPI fields. Treating the ring index as
signed could result in accessing random unrelated memory if the MSB was
set.

Fixes: effd924d2f3b ("drm/amdgpu: untie user ring ids from kernel ring
                      ids v6")
Cc: stable@vger.kernel.org
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Michel Dänzer &lt;michel.daenzer@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: map compute rings by least recently used pipe</title>
<updated>2017-09-28T20:03:22+00:00</updated>
<author>
<name>Andres Rodriguez</name>
<email>andresx7@gmail.com</email>
</author>
<published>2017-09-26T21:43:14+00:00</published>
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<id>urn:sha1:35161bbc135a748dd0a3c822030b3341cdefbd33</id>
<content type='text'>
This patch provides a guarantee that the first n queues allocated by
an application will be on different pipes. Where n is the number of
pipes available from the hardware.

This helps avoid ring aliasing which can result in work executing in
time-sliced mode instead of truly parallel mode.

Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Andres Rodriguez &lt;andresx7@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: use LRU mapping policy for SDMA engines</title>
<updated>2017-05-31T20:49:04+00:00</updated>
<author>
<name>Andres Rodriguez</name>
<email>andresx7@gmail.com</email>
</author>
<published>2017-03-17T18:41:21+00:00</published>
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<id>urn:sha1:90c1130953c1efcc56c79ab810a18c5b72d89669</id>
<content type='text'>
Spreading the load across multiple SDMA engines can increase memory
transfer performance.

Signed-off-by: Andres Rodriguez &lt;andresx7@gmail.com&gt;
Reviewed-by: Nicolai Hähnle &lt;nicolai.haehnle@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
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