hardinfo2.git/modules/devices/riscv/riscv_data.c, branch release-2.0.15

FIX Risc V Supervisor flag handling

2024-03-09T01:10:20+00:00

ADD Risc V new isa Zk,S,U

2024-03-09T00:50:13+00:00

docs: fix simple typo, insensitve -> insensitive

2020-12-22T23:39:53+00:00

There is a small typo in modules/devices/riscv/riscv_data.c. Should read `insensitive` rather than `insensitve`.

x86,arm,riscv: Use gettext contexts and comments for cpu flags

2017-07-19T14:20:33+00:00

* flag defintion strings are grouped into contexts: x86-flag, arm-flag, riscv-ext * a comment is included for translators so that they know what flag the string defines without looking at the source code Signed-off-by: Burt P

x86,arm,riscv: small fixes and flag definition cosmetic tweaks

2017-07-13T02:38:41+00:00

Signed-off-by: Burt P

x86,arm,riscv: make flag definitions translatable

2017-07-13T02:38:41+00:00

Signed-off-by: Burt P

riscv: improve ISA string decoding

2017-07-13T02:38:41+00:00

* Handle unknown future standard extensions better * Handle extension version numbers instead of just ignoring them * Test file riscv_fake_cpuinfo made more tricky Signed-off-by: Burt P

riscv: improvements

2017-07-13T02:38:41+00:00

Signed-off-by: Burt P

riscv: show extension sets

2017-07-13T02:38:41+00:00

Signed-off-by: Burt P