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<title>hardinfo2.git/modules/devices/riscv, branch release-2.1.5</title>
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<id>https://git.gnuabordo.com.br/hardinfo2.git/atom?h=release-2.1.5</id>
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<updated>2024-05-24T10:27:18+00:00</updated>
<entry>
<title>FIX GCC warnings arch/GCC version related</title>
<updated>2024-05-24T10:27:18+00:00</updated>
<author>
<name>hwspeedy</name>
<email>ns@bigbear.dk</email>
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<published>2024-05-24T10:27:18+00:00</published>
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</entry>
<entry>
<title>FIX Risc V Supervisor flag handling</title>
<updated>2024-03-09T01:10:20+00:00</updated>
<author>
<name>hwspeedy</name>
<email>ns@bigbear.dk</email>
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<published>2024-03-09T01:10:20+00:00</published>
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<entry>
<title>ADD Risc V new isa Zk,S,U</title>
<updated>2024-03-09T00:50:13+00:00</updated>
<author>
<name>hwspeedy</name>
<email>ns@bigbear.dk</email>
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<published>2024-03-09T00:50:13+00:00</published>
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<entry>
<title>FIX Risc-V cpu model was translated</title>
<updated>2024-03-05T13:42:01+00:00</updated>
<author>
<name>hwspeedy</name>
<email>ns@bigbear.dk</email>
</author>
<published>2024-03-05T13:42:01+00:00</published>
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</entry>
<entry>
<title>FIX RISC-V processor information</title>
<updated>2024-02-23T23:45:16+00:00</updated>
<author>
<name>hwspeedy</name>
<email>ns@bigbear.dk</email>
</author>
<published>2024-02-23T23:45:16+00:00</published>
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<entry>
<title>LICENSE Changed to GPL2+ for project and source code According to approval from copyright holders - see: https://github.com/lpereira/hardinfo/issues/530 https://github.com/lpereira/hardinfo/issues/707</title>
<updated>2024-02-08T18:52:52+00:00</updated>
<author>
<name>bigbear</name>
<email>ns@bigbear.dk</email>
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<published>2024-02-07T21:10:58+00:00</published>
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</entry>
<entry>
<title>Update copyright information</title>
<updated>2021-11-08T04:36:46+00:00</updated>
<author>
<name>L Pereira</name>
<email>l@tia.mat.br</email>
</author>
<published>2021-11-08T04:36:46+00:00</published>
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<entry>
<title>docs: fix simple typo, insensitve -&gt; insensitive</title>
<updated>2020-12-22T23:39:53+00:00</updated>
<author>
<name>Tim Gates</name>
<email>tim.gates@iress.com</email>
</author>
<published>2020-12-19T22:03:41+00:00</published>
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<content type='text'>
There is a small typo in modules/devices/riscv/riscv_data.c.

Should read `insensitive` rather than `insensitve`.
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</entry>
<entry>
<title>Make MHz translatable in CPU list</title>
<updated>2017-08-11T09:52:21+00:00</updated>
<author>
<name>Burt P</name>
<email>pburt0@gmail.com</email>
</author>
<published>2017-08-11T05:10:52+00:00</published>
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<content type='text'>
It was kindof translatable before, but as part of a messy
use-once c-format string. In this form it is re-usable elsewhere.

Signed-off-by: Burt P &lt;pburt0@gmail.com&gt;
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</entry>
<entry>
<title>Separate processor name and description + count cores and threads</title>
<updated>2017-08-11T09:52:21+00:00</updated>
<author>
<name>Burt P</name>
<email>pburt0@gmail.com</email>
</author>
<published>2017-08-10T16:20:16+00:00</published>
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<id>urn:sha1:05c4a4c9451b7b07577255f7927cec6d70f2cf8d</id>
<content type='text'>
* add cpu_procs_cores_threads() function to get counts from sysfs/topology
* each platform must now provide processor_name() and processor_describe()
* processor_name_default(): returns a list of unique processor-&gt;model_name
* processor_describe_default(): returns "N physical; M cores; L threads"
* processor_describe_by_counting_names(): returns a list of unique
  processor-&gt;model_name with Nx prefix
  (ex: "4x ARM Cortex A53 + 4x ARM Cortex A33")
* x86: _name and _describe use defaults
* arm: _name returns name of SOC, if available, _describe returns
  processor_describe_by_counting_names()
* all other platforms: _name and _describe use defaults
* Computer module summary now shows both name and description for CPU

Signed-off-by: Burt P &lt;pburt0@gmail.com&gt;
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