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authorBurt P <pburt0@gmail.com>2017-07-11 00:21:58 -0500
committerLeandro Pereira <leandro@hardinfo.org>2017-07-12 19:38:41 -0700
commit47009f47a177b4c7e9337e09cf9c4dbe47784110 (patch)
treec72a7c408af619ad636433b6b1df4d43e2ad0e2d
parentbed40787a1fa8e9514be2929dbbec7d3121bbc36 (diff)
x86,arm,riscv: small fixes and flag definition cosmetic tweaks
Signed-off-by: Burt P <pburt0@gmail.com>
-rw-r--r--modules/devices/arm/arm_data.c85
-rw-r--r--modules/devices/riscv/riscv_data.c63
-rw-r--r--modules/devices/riscv/riscv_data.h3
-rw-r--r--modules/devices/x86/processor.c410
4 files changed, 293 insertions, 268 deletions
diff --git a/modules/devices/arm/arm_data.c b/modules/devices/arm/arm_data.c
index 4913713e..0f707b2c 100644
--- a/modules/devices/arm/arm_data.c
+++ b/modules/devices/arm/arm_data.c
@@ -39,46 +39,46 @@ static struct {
char *name, *meaning;
} tab_flag_meaning[] = {
/* arm/hw_cap */
- { "swp", N_("SWP instruction (atomic read-modify-write)") },
- { "half", N_("Half-word loads and stores") },
- { "thumb", N_("Thumb (16-bit instruction set)") },
- { "26bit", N_("26-Bit Model (Processor status register folded into program counter)") },
- { "fastmult", N_("32x32->64-bit multiplication") },
- { "fpa", N_("Floating point accelerator") },
- { "vfp", N_("VFP (early SIMD vector floating point instructions)") },
- { "edsp", N_("DSP extensions (the 'e' variant of the ARM9 CPUs, and all others above)") },
- { "java", N_("Jazelle (Java bytecode accelerator)") },
- { "iwmmxt", N_("SIMD instructions similar to Intel MMX") },
- { "crunch", N_("MaverickCrunch coprocessor (if kernel support enabled)") },
- { "thumbee", N_("ThumbEE") },
- { "neon", N_("Advanced SIMD/NEON on AArch32") },
- { "evtstrm", N_("kernel event stream using generic architected timer") },
- { "vfpv3", N_("VFP version 3") },
- { "vfpv3d16", N_("VFP version 3 with 16 D-registers") },
- { "vfpv4", N_("VFP version 4 with fast context switching") },
- { "vfpd32", N_("VFP with 32 D-registers") },
- { "tls", N_("TLS register") },
- { "idiva", N_("SDIV and UDIV hardware division in ARM mode") },
- { "idivt", N_("SDIV and UDIV hardware division in Thumb mode") },
- { "lpae", N_("40-bit Large Physical Address Extension") },
+ { "swp", N_("SWP instruction (atomic read-modify-write)") },
+ { "half", N_("Half-word loads and stores") },
+ { "thumb", N_("Thumb (16-bit instruction set)") },
+ { "26bit", N_("26-Bit Model (Processor status register folded into program counter)") },
+ { "fastmult", N_("32x32->64-bit multiplication") },
+ { "fpa", N_("Floating point accelerator") },
+ { "vfp", N_("VFP (early SIMD vector floating point instructions)") },
+ { "edsp", N_("DSP extensions (the 'e' variant of the ARM9 CPUs, and all others above)") },
+ { "java", N_("Jazelle (Java bytecode accelerator)") },
+ { "iwmmxt", N_("SIMD instructions similar to Intel MMX") },
+ { "crunch", N_("MaverickCrunch coprocessor (if kernel support enabled)") },
+ { "thumbee", N_("ThumbEE") },
+ { "neon", N_("Advanced SIMD/NEON on AArch32") },
+ { "evtstrm", N_("kernel event stream using generic architected timer") },
+ { "vfpv3", N_("VFP version 3") },
+ { "vfpv3d16", N_("VFP version 3 with 16 D-registers") },
+ { "vfpv4", N_("VFP version 4 with fast context switching") },
+ { "vfpd32", N_("VFP with 32 D-registers") },
+ { "tls", N_("TLS register") },
+ { "idiva", N_("SDIV and UDIV hardware division in ARM mode") },
+ { "idivt", N_("SDIV and UDIV hardware division in Thumb mode") },
+ { "lpae", N_("40-bit Large Physical Address Extension") },
/* arm/hw_cap2 */
- { "pmull", N_("64x64->128-bit F2m multiplication (arch>8)") },
- { "aes", N_("Crypto:AES (arch>8)") },
- { "sha1", N_("Crypto:SHA1 (arch>8)") },
- { "sha2", N_("Crypto:SHA2 (arch>8)") },
- { "crc32", N_("CRC32 checksum instructions (arch>8)") },
+ { "pmull", N_("64x64->128-bit F2m multiplication (arch>8)") },
+ { "aes", N_("Crypto:AES (arch>8)") },
+ { "sha1", N_("Crypto:SHA1 (arch>8)") },
+ { "sha2", N_("Crypto:SHA2 (arch>8)") },
+ { "crc32", N_("CRC32 checksum instructions (arch>8)") },
/* arm64/hw_cap */
- { "fp", "" },
- { "asimd", N_("Advanced SIMD/NEON on AArch64 (arch>8)") },
- { "atomics", "" },
- { "fphp", "" },
- { "asimdhp", "" },
- { "cpuid", "" },
- { "asimdrdm", "" },
- { "jscvt", "" },
- { "fcma", "" },
- { "lrcpc", "" },
- { NULL, NULL},
+ { "fp", NULL },
+ { "asimd", N_("Advanced SIMD/NEON on AArch64 (arch>8)") },
+ { "atomics", NULL },
+ { "fphp", NULL },
+ { "asimdhp", NULL },
+ { "cpuid", NULL },
+ { "asimdrdm", NULL },
+ { "jscvt", NULL },
+ { "fcma", NULL },
+ { "lrcpc", NULL },
+ { NULL, NULL }
};
static struct {
@@ -149,8 +149,11 @@ const char *arm_flag_meaning(const char *flag) {
int i = 0;
if (flag)
while(tab_flag_meaning[i].name != NULL) {
- if (strcmp(tab_flag_meaning[i].name, flag) == 0)
- return _(tab_flag_meaning[i].meaning);
+ if (strcmp(tab_flag_meaning[i].name, flag) == 0) {
+ if (tab_flag_meaning[i].meaning != NULL)
+ return _(tab_flag_meaning[i].meaning);
+ else return NULL;
+ }
i++;
}
return NULL;
@@ -226,7 +229,7 @@ char *arm_decoded_name(const char *imp, const char *part, const char *var, const
p = strtol(rev, NULL, 0);
imp_name = (char*) arm_implementer(imp);
part_desc = (char*) arm_part(imp, part);
- arch_name = (char *) arm_arch(arch);
+ arch_name = (char*) arm_arch(arch);
if (imp_name || part_desc) {
if (arch_name != arch)
sprintf(dnbuff, "%s %s r%dp%d (%s)",
diff --git a/modules/devices/riscv/riscv_data.c b/modules/devices/riscv/riscv_data.c
index b61a85de..bd4266eb 100644
--- a/modules/devices/riscv/riscv_data.c
+++ b/modules/devices/riscv/riscv_data.c
@@ -21,6 +21,7 @@
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
+#include <ctype.h>
#include "riscv_data.h"
#ifndef _
@@ -33,27 +34,42 @@
static struct {
char *name, *meaning;
} tab_ext_meaning[] = {
- { "RV32", N_("32-bit") },
- { "RV64", N_("64-bit") },
- { "RV128", N_("128-bit") },
- { "E", N_("Base embedded integer instructions (15 registers)") },
- { "I", N_("Base integer instructions (31 registers)") },
- { "M", N_("Hardware integer multiply and divide") },
- { "A", N_("Atomic memory operations") },
- { "C", N_("Compressed 16-bit instructions") },
- { "F", N_("Floating-point instructions, single-precision") },
- { "D", N_("Floating-point instructions, double-precision") },
- { "Q", N_("Floating-point instructions, quad-precision") },
- { "B", N_("Bit manipulation instructions") },
- { "V", N_("Vector operations") },
- { "T", N_("Transactional memory") },
- { "P", N_("Packed SIMD instructions") },
- { "L", N_("Decimal floating-point instructions") },
- { "J", N_("Dynamically translated languages") },
- { "N", N_("User-level interrupts") },
+ { "RV32", N_("RISC-V 32-bit") },
+ { "RV64", N_("RISC-V 64-bit") },
+ { "RV128", N_("RISC-V 128-bit") },
+ { "E", N_("Base embedded integer instructions (15 registers)") },
+ { "I", N_("Base integer instructions (31 registers)") },
+ { "M", N_("Hardware integer multiply and divide") },
+ { "A", N_("Atomic memory operations") },
+ { "C", N_("Compressed 16-bit instructions") },
+ { "F", N_("Floating-point instructions, single-precision") },
+ { "D", N_("Floating-point instructions, double-precision") },
+ { "Q", N_("Floating-point instructions, quad-precision") },
+ { "B", N_("Bit manipulation instructions") },
+ { "V", N_("Vector operations") },
+ { "T", N_("Transactional memory") },
+ { "P", N_("Packed SIMD instructions") },
+ { "L", N_("Decimal floating-point instructions") },
+ { "J", N_("Dynamically translated languages") },
+ { "N", N_("User-level interrupts") },
{ NULL, NULL }
};
+static char all_extensions[1024] = "";
+
+#define APPEND_EXT(f) strcat(all_extensions, f); strcat(all_extensions, " ");
+const char *riscv_ext_list() {
+ int i = 0, built = 0;
+ built = strlen(all_extensions);
+ if (!built) {
+ while(tab_ext_meaning[i].name != NULL) {
+ APPEND_EXT(tab_ext_meaning[i].name);
+ i++;
+ }
+ }
+ return all_extensions;
+}
+
const char *riscv_ext_meaning(const char *ext) {
int i = 0, l = 0;
char *c = NULL;
@@ -64,8 +80,11 @@ const char *riscv_ext_meaning(const char *ext) {
else
l = strlen(ext);
while(tab_ext_meaning[i].name != NULL) {
- if (strncasecmp(tab_ext_meaning[i].name, ext, l) == 0)
- return _(tab_ext_meaning[i].meaning);
+ if (strncasecmp(tab_ext_meaning[i].name, ext, l) == 0) {
+ if (tab_ext_meaning[i].meaning != NULL)
+ return _(tab_ext_meaning[i].meaning);
+ else return NULL;
+ }
i++;
}
}
@@ -83,7 +102,7 @@ const char *riscv_ext_meaning(const char *ext) {
static int riscv_isa_next(const char *isap, char *flag) {
char *p = NULL, *start = NULL;
char *next_sep = NULL, *next_digit = NULL;
- int skip_len = 0, tag_len = 0, ver_len = 0, has_ver = 0;
+ int skip_len = 0, tag_len = 0, ver_len = 0;
char ext_str[32], ver_str[32];
if (isap == NULL)
@@ -174,7 +193,7 @@ char *riscv_isa_to_flags(const char *isa) {
else if ( RV_CHECK_FOR("128") )
{ ADD_EXT_FLAG("RV128"); ps += 3; }
- while(tl = riscv_isa_next(ps, flag_buf)) {
+ while( (tl = riscv_isa_next(ps, flag_buf)) ) {
if (flag_buf[0] == 'G') { /* G = IMAFD */
flag_buf[0] = 'I'; ADD_EXT_FLAG(flag_buf);
flag_buf[0] = 'M'; ADD_EXT_FLAG(flag_buf);
diff --git a/modules/devices/riscv/riscv_data.h b/modules/devices/riscv/riscv_data.h
index 323c3722..1d3a0a48 100644
--- a/modules/devices/riscv/riscv_data.h
+++ b/modules/devices/riscv/riscv_data.h
@@ -24,6 +24,9 @@
/* convert RISC-V ISA string to flags list */
char *riscv_isa_to_flags(const char *isa);
+/* all known extensions as flags list */
+const char *riscv_ext_list(void);
+
/* get meaning of flag */
const char *riscv_ext_meaning(const char *ext);
diff --git a/modules/devices/x86/processor.c b/modules/devices/x86/processor.c
index c8db6382..9adfe9c8 100644
--- a/modules/devices/x86/processor.c
+++ b/modules/devices/x86/processor.c
@@ -272,6 +272,8 @@ GSList *processor_scan(void)
g_strfreev(tmp);
}
+ fclose(cpuinfo);
+
/* finish last */
if (processor)
procs = g_slist_append(procs, processor);
@@ -319,8 +321,6 @@ GSList *processor_scan(void)
processor->cpu_mhz = processor->cpufreq->cpukhz_max / 1000;
}
- fclose(cpuinfo);
-
return procs;
}
@@ -336,228 +336,228 @@ static struct {
} flag_meaning[] = {
/* Intel-defined CPU features, CPUID level 0x00000001 (edx)
* See also Wikipedia and table 2-27 in Intel Advanced Vector Extensions Programming Reference */
- { "fpu", N_("Onboard FPU (floating point support)") },
- { "vme", N_("Virtual 8086 mode enhancements") },
- { "de", N_("Debugging Extensions (CR4.DE)") },
- { "pse", N_("Page Size Extensions (4MB memory pages)") },
- { "tsc", N_("Time Stamp Counter (RDTSC)") },
- { "msr", N_("Model-Specific Registers (RDMSR, WRMSR)") },
- { "pae", N_("Physical Address Extensions (support for more than 4GB of RAM)") },
- { "mce", N_("Machine Check Exception") },
- { "cx8", N_("CMPXCHG8 instruction (64-bit compare-and-swap)") },
- { "apic", N_("Onboard APIC") },
- { "sep", N_("SYSENTER/SYSEXIT") },
- { "mtrr", N_("Memory Type Range Registers") },
- { "pge", N_("Page Global Enable (global bit in PDEs and PTEs)") },
- { "mca", N_("Machine Check Architecture") },
- { "cmov", N_("CMOV instructions (conditional move) (also FCMOV)") },
- { "pat", N_("Page Attribute Table") },
- { "pse36", N_("36-bit PSEs (huge pages)") },
- { "pn", N_("Processor serial number") },
- { "clflush", N_("Cache Line Flush instruction") },
- { "dts", N_("Debug Store (buffer for debugging and profiling instructions)") },
- { "acpi", N_("ACPI via MSR (temperature monitoring and clock speed modulation)") },
- { "mmx", N_("Multimedia Extensions") },
- { "fxsr", N_("FXSAVE/FXRSTOR, CR4.OSFXSR") },
- { "sse", N_("Intel SSE vector instructions") },
- { "sse2", N_("SSE2") },
- { "ss", N_("CPU self snoop") },
- { "ht", N_("Hyper-Threading") },
- { "tm", N_("Automatic clock control (Thermal Monitor)") },
- { "ia64", N_("Intel Itanium Architecture 64-bit (not to be confused with Intel's 64-bit x86 architecture with flag x86-64 or \"AMD64\" bit indicated by flag lm)") },
- { "pbe", N_("Pending Break Enable (PBE# pin) wakeup support") },
+ { "fpu", N_("Onboard FPU (floating point support)") },
+ { "vme", N_("Virtual 8086 mode enhancements") },
+ { "de", N_("Debugging Extensions (CR4.DE)") },
+ { "pse", N_("Page Size Extensions (4MB memory pages)") },
+ { "tsc", N_("Time Stamp Counter (RDTSC)") },
+ { "msr", N_("Model-Specific Registers (RDMSR, WRMSR)") },
+ { "pae", N_("Physical Address Extensions (support for more than 4GB of RAM)") },
+ { "mce", N_("Machine Check Exception") },
+ { "cx8", N_("CMPXCHG8 instruction (64-bit compare-and-swap)") },
+ { "apic", N_("Onboard APIC") },
+ { "sep", N_("SYSENTER/SYSEXIT") },
+ { "mtrr", N_("Memory Type Range Registers") },
+ { "pge", N_("Page Global Enable (global bit in PDEs and PTEs)") },
+ { "mca", N_("Machine Check Architecture") },
+ { "cmov", N_("CMOV instructions (conditional move) (also FCMOV)") },
+ { "pat", N_("Page Attribute Table") },
+ { "pse36", N_("36-bit PSEs (huge pages)") },
+ { "pn", N_("Processor serial number") },
+ { "clflush", N_("Cache Line Flush instruction") },
+ { "dts", N_("Debug Store (buffer for debugging and profiling instructions), or alternately: digital thermal sensor") },
+ { "acpi", N_("ACPI via MSR (temperature monitoring and clock speed modulation)") },
+ { "mmx", N_("Multimedia Extensions") },
+ { "fxsr", N_("FXSAVE/FXRSTOR, CR4.OSFXSR") },
+ { "sse", N_("Intel SSE vector instructions") },
+ { "sse2", N_("SSE2") },
+ { "ss", N_("CPU self snoop") },
+ { "ht", N_("Hyper-Threading") },
+ { "tm", N_("Automatic clock control (Thermal Monitor)") },
+ { "ia64", N_("Intel Itanium Architecture 64-bit (not to be confused with Intel's 64-bit x86 architecture with flag x86-64 or \"AMD64\" bit indicated by flag lm)") },
+ { "pbe", N_("Pending Break Enable (PBE# pin) wakeup support") },
/* AMD-defined CPU features, CPUID level 0x80000001
* See also Wikipedia and table 2-23 in Intel Advanced Vector Extensions Programming Reference */
- { "syscall", N_("SYSCALL (Fast System Call) and SYSRET (Return From Fast System Call)") },
- { "mp", N_("Multiprocessing Capable.") },
- { "nx", N_("Execute Disable") },
- { "mmxext", N_("AMD MMX extensions") },
- { "fxsr_opt", N_("FXSAVE/FXRSTOR optimizations") },
- { "pdpe1gb", N_("One GB pages (allows hugepagesz=1G)") },
- { "rdtscp", N_("Read Time-Stamp Counter and Processor ID") },
- { "lm", N_("Long Mode (x86-64: amd64, also known as Intel 64, i.e. 64-bit capable)") },
- { "3dnow", N_("3DNow! (AMD vector instructions, competing with Intel's SSE1)") },
- { "3dnowext", N_("AMD 3DNow! extensions") },
+ { "syscall", N_("SYSCALL (Fast System Call) and SYSRET (Return From Fast System Call)") },
+ { "mp", N_("Multiprocessing Capable.") },
+ { "nx", N_("Execute Disable") },
+ { "mmxext", N_("AMD MMX extensions") },
+ { "fxsr_opt", N_("FXSAVE/FXRSTOR optimizations") },
+ { "pdpe1gb", N_("One GB pages (allows hugepagesz=1G)") },
+ { "rdtscp", N_("Read Time-Stamp Counter and Processor ID") },
+ { "lm", N_("Long Mode (x86-64: amd64, also known as Intel 64, i.e. 64-bit capable)") },
+ { "3dnow", N_("3DNow! (AMD vector instructions, competing with Intel's SSE1)") },
+ { "3dnowext", N_("AMD 3DNow! extensions") },
/* Transmeta-defined CPU features, CPUID level 0x80860001 */
- { "recovery", N_("CPU in recovery mode") },
- { "longrun", N_("Longrun power control") },
- { "lrti", N_("LongRun table interface") },
+ { "recovery", N_("CPU in recovery mode") },
+ { "longrun", N_("Longrun power control") },
+ { "lrti", N_("LongRun table interface") },
/* Other features, Linux-defined mapping */
- { "cxmmx", N_("Cyrix MMX extensions") },
- { "k6_mtrr", N_("AMD K6 nonstandard MTRRs") },
- { "cyrix_arr", N_("Cyrix ARRs (= MTRRs)") },
- { "centaur_mcr", N_("Centaur MCRs (= MTRRs)") },
- { "constant_tsc", N_("TSC ticks at a constant rate") },
- { "up", N_("SMP kernel running on UP") },
- { "art", N_("Always-Running Timer") },
- { "arch_perfmon", N_("Intel Architectural PerfMon") },
- { "pebs", N_("Precise-Event Based Sampling") },
- { "bts", N_("Branch Trace Store") },
- { "rep_good", N_("rep microcode works well") },
- { "acc_power", N_("AMD accumulated power mechanism") },
- { "nopl", N_("The NOPL (0F 1F) instructions") },
- { "xtopology", N_("cpu topology enum extensions") },
- { "tsc_reliable", N_("TSC is known to be reliable") },
- { "nonstop_tsc", N_("TSC does not stop in C states") },
- { "extd_apicid", N_("has extended APICID (8 bits)") },
- { "amd_dcm", N_("multi-node processor") },
- { "aperfmperf", N_("APERFMPERF") },
- { "eagerfpu", N_("Non lazy FPU restore") },
- { "nonstop_tsc_s3", N_("TSC doesn't stop in S3 state") },
- { "mce_recovery", N_("CPU has recoverable machine checks") },
+ { "cxmmx", N_("Cyrix MMX extensions") },
+ { "k6_mtrr", N_("AMD K6 nonstandard MTRRs") },
+ { "cyrix_arr", N_("Cyrix ARRs (= MTRRs)") },
+ { "centaur_mcr", N_("Centaur MCRs (= MTRRs)") },
+ { "constant_tsc", N_("TSC ticks at a constant rate") },
+ { "up", N_("SMP kernel running on UP") },
+ { "art", N_("Always-Running Timer") },
+ { "arch_perfmon", N_("Intel Architectural PerfMon") },
+ { "pebs", N_("Precise-Event Based Sampling") },
+ { "bts", N_("Branch Trace Store") },
+ { "rep_good", N_("rep microcode works well") },
+ { "acc_power", N_("AMD accumulated power mechanism") },
+ { "nopl", N_("The NOPL (0F 1F) instructions") },
+ { "xtopology", N_("cpu topology enum extensions") },
+ { "tsc_reliable", N_("TSC is known to be reliable") },
+ { "nonstop_tsc", N_("TSC does not stop in C states") },
+ { "extd_apicid", N_("has extended APICID (8 bits)") },
+ { "amd_dcm", N_("multi-node processor") },
+ { "aperfmperf", N_("APERFMPERF") },
+ { "eagerfpu", N_("Non lazy FPU restore") },
+ { "nonstop_tsc_s3", N_("TSC doesn't stop in S3 state") },
+ { "mce_recovery", N_("CPU has recoverable machine checks") },
/* Intel-defined CPU features, CPUID level 0x00000001 (ecx)
* See also Wikipedia and table 2-26 in Intel Advanced Vector Extensions Programming Reference */
- { "pni", N_("SSE-3 (“Prescott New Instructions”)") },
- { "pclmulqdq", N_("Perform a Carry-Less Multiplication of Quadword instruction — accelerator for GCM)") },
- { "dtes64", N_("64-bit Debug Store") },
- { "monitor", N_("Monitor/Mwait support (Intel SSE3 supplements)") },
- { "ds_cpl", N_("CPL Qual. Debug Store") },
- { "vmx: Hardware virtualization", N_("Intel VMX") },
- { "smx: Safer mode", N_("TXT (TPM support)") },
- { "est", N_("Enhanced SpeedStep") },
- { "tm2", N_("Thermal Monitor 2") },
- { "ssse3", N_("Supplemental SSE-3") },
- { "cid", N_("Context ID") },
- { "sdbg", N_("silicon debug") },
- { "fma", N_("Fused multiply-add") },
- { "cx16", N_("CMPXCHG16B") },
- { "xtpr", N_("Send Task Priority Messages") },
- { "pdcm", N_("Performance Capabilities") },
- { "pcid", N_("Process Context Identifiers") },
- { "dca", N_("Direct Cache Access") },
- { "sse4_1", N_("SSE-4.1") },
- { "sse4_2", N_("SSE-4.2") },
- { "x2apic", N_("x2APIC") },
- { "movbe", N_("Move Data After Swapping Bytes instruction") },
- { "popcnt", N_("Return the Count of Number of Bits Set to 1 instruction (Hamming weight, i.e. bit count)") },
- { "tsc_deadline_timer", N_("Tsc deadline timer") },
- { "aes/aes-ni", N_("Advanced Encryption Standard (New Instructions)") },
- { "xsave", N_("Save Processor Extended States: also provides XGETBY,XRSTOR,XSETBY") },
- { "avx", N_("Advanced Vector Extensions") },
- { "f16c", N_("16-bit fp conversions (CVT16)") },
- { "rdrand", N_("Read Random Number from hardware random number generator instruction") },
- { "hypervisor", N_("Running on a hypervisor") },
+ { "pni", N_("SSE-3 (“Prescott New Instructions”)") },
+ { "pclmulqdq", N_("Perform a Carry-Less Multiplication of Quadword instruction — accelerator for GCM)") },
+ { "dtes64", N_("64-bit Debug Store") },
+ { "monitor", N_("Monitor/Mwait support (Intel SSE3 supplements)") },
+ { "ds_cpl", N_("CPL Qual. Debug Store") },
+ { "vmx", N_("Hardware virtualization, Intel VMX") },
+ { "smx", N_("Safer mode TXT (TPM support)") },
+ { "est", N_("Enhanced SpeedStep") },
+ { "tm2", N_("Thermal Monitor 2") },
+ { "ssse3", N_("Supplemental SSE-3") },
+ { "cid", N_("Context ID") },
+ { "sdbg", N_("silicon debug") },
+ { "fma", N_("Fused multiply-add") },
+ { "cx16", N_("CMPXCHG16B") },
+ { "xtpr", N_("Send Task Priority Messages") },
+ { "pdcm", N_("Performance Capabilities") },
+ { "pcid", N_("Process Context Identifiers") },
+ { "dca", N_("Direct Cache Access") },
+ { "sse4_1", N_("SSE-4.1") },
+ { "sse4_2", N_("SSE-4.2") },
+ { "x2apic", N_("x2APIC") },
+ { "movbe", N_("Move Data After Swapping Bytes instruction") },
+ { "popcnt", N_("Return the Count of Number of Bits Set to 1 instruction (Hamming weight, i.e. bit count)") },
+ { "tsc_deadline_timer", N_("Tsc deadline timer") },
+ { "aes/aes-ni", N_("Advanced Encryption Standard (New Instructions)") },
+ { "xsave", N_("Save Processor Extended States: also provides XGETBY,XRSTOR,XSETBY") },
+ { "avx", N_("Advanced Vector Extensions") },
+ { "f16c", N_("16-bit fp conversions (CVT16)") },
+ { "rdrand", N_("Read Random Number from hardware random number generator instruction") },
+ { "hypervisor", N_("Running on a hypervisor") },
/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001 */
- { "rng", N_("Random Number Generator present (xstore)") },
- { "rng_en", N_("Random Number Generator enabled") },
- { "ace", N_("on-CPU crypto (xcrypt)") },
- { "ace_en", N_("on-CPU crypto enabled") },
- { "ace2", N_("Advanced Cryptography Engine v2") },
- { "ace2_en", N_("ACE v2 enabled") },
- { "phe", N_("PadLock Hash Engine") },
- { "phe_en", N_("PHE enabled") },
- { "pmm", N_("PadLock Montgomery Multiplier") },
- { "pmm_en", N_("PMM enabled") },
+ { "rng", N_("Random Number Generator present (xstore)") },
+ { "rng_en", N_("Random Number Generator enabled") },
+ { "ace", N_("on-CPU crypto (xcrypt)") },
+ { "ace_en", N_("on-CPU crypto enabled") },
+ { "ace2", N_("Advanced Cryptography Engine v2") },
+ { "ace2_en", N_("ACE v2 enabled") },
+ { "phe", N_("PadLock Hash Engine") },
+ { "phe_en", N_("PHE enabled") },
+ { "pmm", N_("PadLock Montgomery Multiplier") },
+ { "pmm_en", N_("PMM enabled") },
/* More extended AMD flags: CPUID level 0x80000001, ecx */
- { "lahf_lm", N_("Load AH from Flags (LAHF) and Store AH into Flags (SAHF) in long mode") },
- { "cmp_legacy", N_("If yes HyperThreading not valid") },
- { "svm", N_("\"Secure virtual machine\": AMD-V") },
- { "extapic", N_("Extended APIC space") },
- { "cr8_legacy", N_("CR8 in 32-bit mode") },
- { "abm", N_("Advanced Bit Manipulation") },
- { "sse4a", N_("SSE-4A") },
- { "misalignsse", N_("indicates if a general-protection exception (#GP) is generated when some legacy SSE instructions operate on unaligned data. Also depends on CR0 and Alignment Checking bit") },
- { "3dnowprefetch", N_("3DNow prefetch instructions") },
- { "osvw", N_("indicates OS Visible Workaround, which allows the OS to work around processor errata.") },
- { "ibs", N_("Instruction Based Sampling") },
- { "xop", N_("extended AVX instructions") },
- { "skinit", N_("SKINIT/STGI instructions") },
- { "wdt", N_("Watchdog timer") },
- { "lwp", N_("Light Weight Profiling") },
- { "fma4", N_("4 operands MAC instructions") },
- { "tce", N_("translation cache extension") },
- { "nodeid_msr", N_("NodeId MSR") },
- { "tbm", N_("Trailing Bit Manipulation") },
- { "topoext", N_("Topology Extensions CPUID leafs") },
- { "perfctr_core", N_("Core Performance Counter Extensions") },
- { "perfctr_nb", N_("NB Performance Counter Extensions") },
- { "bpext", N_("data breakpoint extension") },
- { "ptsc", N_("performance time-stamp counter") },
- { "perfctr_l2", N_("L2 Performance Counter Extensions") },
- { "mwaitx", N_("MWAIT extension (MONITORX/MWAITX)") },
+ { "lahf_lm", N_("Load AH from Flags (LAHF) and Store AH into Flags (SAHF) in long mode") },
+ { "cmp_legacy", N_("If yes HyperThreading not valid") },
+ { "svm", N_("\"Secure virtual machine\": AMD-V") },
+ { "extapic", N_("Extended APIC space") },
+ { "cr8_legacy", N_("CR8 in 32-bit mode") },
+ { "abm", N_("Advanced Bit Manipulation") },
+ { "sse4a", N_("SSE-4A") },
+ { "misalignsse", N_("indicates if a general-protection exception (#GP) is generated when some legacy SSE instructions operate on unaligned data. Also depends on CR0 and Alignment Checking bit") },
+ { "3dnowprefetch", N_("3DNow prefetch instructions") },
+ { "osvw", N_("indicates OS Visible Workaround, which allows the OS to work around processor errata.") },
+ { "ibs", N_("Instruction Based Sampling") },
+ { "xop", N_("extended AVX instructions") },
+ { "skinit", N_("SKINIT/STGI instructions") },
+ { "wdt", N_("Watchdog timer") },
+ { "lwp", N_("Light Weight Profiling") },
+ { "fma4", N_("4 operands MAC instructions") },
+ { "tce", N_("translation cache extension") },
+ { "nodeid_msr", N_("NodeId MSR") },
+ { "tbm", N_("Trailing Bit Manipulation") },
+ { "topoext", N_("Topology Extensions CPUID leafs") },
+ { "perfctr_core", N_("Core Performance Counter Extensions") },
+ { "perfctr_nb", N_("NB Performance Counter Extensions") },
+ { "bpext", N_("data breakpoint extension") },
+ { "ptsc", N_("performance time-stamp counter") },
+ { "perfctr_l2", N_("L2 Performance Counter Extensions") },
+ { "mwaitx", N_("MWAIT extension (MONITORX/MWAITX)") },
/* Auxiliary flags: Linux defined - For features scattered in various CPUID levels */
- { "cpb", N_("AMD Core Performance Boost") },
- { "epb", N_("IA32_ENERGY_PERF_BIAS support") },
- { "hw_pstate", N_("AMD HW-PState") },
- { "proc_feedback", N_("AMD ProcFeedbackInterface") },
- { "intel_pt", N_("Intel Processor Tracing") },
+ { "cpb", N_("AMD Core Performance Boost") },
+ { "epb", N_("IA32_ENERGY_PERF_BIAS support") },
+ { "hw_pstate", N_("AMD HW-PState") },
+ { "proc_feedback", N_("AMD ProcFeedbackInterface") },
+ { "intel_pt", N_("Intel Processor Tracing") },
/* Virtualization flags: Linux defined */
- { "tpr_shadow", N_("Intel TPR Shadow") },
- { "vnmi", N_("Intel Virtual NMI") },
- { "flexpriority", N_("Intel FlexPriority") },
- { "ept", N_("Intel Extended Page Table") },
- { "vpid", N_("Intel Virtual Processor ID") },
- { "vmmcall", N_("prefer VMMCALL to VMCALL") },
+ { "tpr_shadow", N_("Intel TPR Shadow") },
+ { "vnmi", N_("Intel Virtual NMI") },
+ { "flexpriority", N_("Intel FlexPriority") },
+ { "ept", N_("Intel Extended Page Table") },
+ { "vpid", N_("Intel Virtual Processor ID") },
+ { "vmmcall", N_("prefer VMMCALL to VMCALL") },
/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx) */
- { "fsgsbase", N_("{RD/WR}{FS/GS}BASE instructions") },
- { "tsc_adjust", N_("TSC adjustment MSR") },
- { "bmi1", N_("1st group bit manipulation extensions") },
- { "hle", N_("Hardware Lock Elision") },
- { "avx2", N_("AVX2 instructions") },
- { "smep", N_("Supervisor Mode Execution Protection") },
- { "bmi2", N_("2nd group bit manipulation extensions") },
- { "erms", N_("Enhanced REP MOVSB/STOSB") },
- { "invpcid", N_("Invalidate Processor Context ID") },
- { "rtm", N_("Restricted Transactional Memory") },
- { "cqm", N_("Cache QoS Monitoring") },
- { "mpx", N_("Memory Protection Extension") },
- { "avx512f", N_("AVX-512 foundation") },
- { "avx512dq", N_("AVX-512 Double/Quad instructions") },
- { "rdseed", N_("The RDSEED instruction") },
- { "adx", N_("The ADCX and ADOX instructions") },
- { "smap", N_("Supervisor Mode Access Prevention") },
- { "clflushopt", N_("CLFLUSHOPT instruction") },
- { "clwb", N_("CLWB instruction") },
- { "avx512pf", N_("AVX-512 Prefetch") },
- { "avx512er", N_("AVX-512 Exponential and Reciprocal") },
- { "avx512cd", N_("AVX-512 Conflict Detection") },
- { "sha_ni", N_("SHA1/SHA256 Instruction Extensions") },
- { "avx512bw", N_("AVX-512 Byte/Word instructions") },
- { "avx512vl", N_("AVX-512 128/256 Vector Length extensions") },
+ { "fsgsbase", N_("{RD/WR}{FS/GS}BASE instructions") },
+ { "tsc_adjust", N_("TSC adjustment MSR") },
+ { "bmi1", N_("1st group bit manipulation extensions") },
+ { "hle", N_("Hardware Lock Elision") },
+ { "avx2", N_("AVX2 instructions") },
+ { "smep", N_("Supervisor Mode Execution Protection") },
+ { "bmi2", N_("2nd group bit manipulation extensions") },
+ { "erms", N_("Enhanced REP MOVSB/STOSB") },
+ { "invpcid", N_("Invalidate Processor Context ID") },
+ { "rtm", N_("Restricted Transactional Memory") },
+ { "cqm", N_("Cache QoS Monitoring") },
+ { "mpx", N_("Memory Protection Extension") },
+ { "avx512f", N_("AVX-512 foundation") },
+ { "avx512dq", N_("AVX-512 Double/Quad instructions") },
+ { "rdseed", N_("The RDSEED instruction") },
+ { "adx", N_("The ADCX and ADOX instructions") },
+ { "smap", N_("Supervisor Mode Access Prevention") },
+ { "clflushopt", N_("CLFLUSHOPT instruction") },
+ { "clwb", N_("CLWB instruction") },
+ { "avx512pf", N_("AVX-512 Prefetch") },
+ { "avx512er", N_("AVX-512 Exponential and Reciprocal") },
+ { "avx512cd", N_("AVX-512 Conflict Detection") },
+ { "sha_ni", N_("SHA1/SHA256 Instruction Extensions") },
+ { "avx512bw", N_("AVX-512 Byte/Word instructions") },
+ { "avx512vl", N_("AVX-512 128/256 Vector Length extensions") },
/* Extended state features, CPUID level 0x0000000d:1 (eax) */
- { "xsaveopt", N_("Optimized XSAVE") },
- { "xsavec", N_("XSAVEC") },
- { "xgetbv1", N_("XGETBV with ECX = 1") },
- { "xsaves", N_("XSAVES/XRSTORS") },
+ { "xsaveopt", N_("Optimized XSAVE") },
+ { "xsavec", N_("XSAVEC") },
+ { "xgetbv1", N_("XGETBV with ECX = 1") },
+ { "xsaves", N_("XSAVES/XRSTORS") },
/* Intel-defined CPU QoS sub-leaf, CPUID level 0x0000000F:0 (edx) */
- { "cqm_llc", N_("LLC QoS") },
+ { "cqm_llc", N_("LLC QoS") },
/* Intel-defined CPU QoS sub-leaf, CPUID level 0x0000000F:1 (edx) */
- { "cqm_occup_llc", N_("LLC occupancy monitoring") },
- { "cqm_mbm_total", N_("LLC total MBM monitoring") },
- { "cqm_mbm_local", N_("LLC local MBM monitoring") },
+ { "cqm_occup_llc", N_("LLC occupancy monitoring") },
+ { "cqm_mbm_total", N_("LLC total MBM monitoring") },
+ { "cqm_mbm_local", N_("LLC local MBM monitoring") },
/* AMD-defined CPU features, CPUID level 0x80000008 (ebx) */
- { "clzero", N_("CLZERO instruction") },
- { "irperf", N_("instructions retired performance counter") },
+ { "clzero", N_("CLZERO instruction") },
+ { "irperf", N_("instructions retired performance counter") },
/* Thermal and Power Management leaf, CPUID level 0x00000006 (eax) */
- { "dtherm (formerly dts)", N_("digital thermal sensor") },
- { "ida", N_("Intel Dynamic Acceleration") },
- { "arat", N_("Always Running APIC Timer") },
- { "pln", N_("Intel Power Limit Notification") },
- { "pts", N_("Intel Package Thermal Status") },
- { "hwp", N_("Intel Hardware P-states") },
- { "hwp_notify", N_("HWP notification") },
- { "hwp_act_window", N_("HWP Activity Window") },
- { "hwp_epp", N_("HWP Energy Performance Preference") },
- { "hwp_pkg_req", N_("HWP package-level request") },
+ { "dtherm", N_("digital thermal sensor") }, /* formerly dts */
+ { "ida", N_("Intel Dynamic Acceleration") },
+ { "arat", N_("Always Running APIC Timer") },
+ { "pln", N_("Intel Power Limit Notification") },
+ { "pts", N_("Intel Package Thermal Status") },
+ { "hwp", N_("Intel Hardware P-states") },
+ { "hwp_notify", N_("HWP notification") },
+ { "hwp_act_window", N_("HWP Activity Window") },
+ { "hwp_epp", N_("HWP Energy Performance Preference") },
+ { "hwp_pkg_req", N_("HWP package-level request") },
/* AMD SVM Feature Identification, CPUID level 0x8000000a (edx) */
- { "npt", N_("AMD Nested Page Table support") },
- { "lbrv", N_("AMD LBR Virtualization support") },
- { "svm_lock", N_("AMD SVM locking MSR") },
- { "nrip_save", N_("AMD SVM next_rip save") },
- { "tsc_scale", N_("AMD TSC scaling support") },
- { "vmcb_clean", N_("AMD VMCB clean bits support") },
- { "flushbyasid", N_("AMD flush-by-ASID support") },
- { "decodeassists", N_("AMD Decode Assists support") },
- { "pausefilter", N_("AMD filtered pause intercept") },
- { "pfthreshold", N_("AMD pause filter threshold") },
- { "avic", N_("Virtual Interrupt Controller") },
+ { "npt", N_("AMD Nested Page Table support") },
+ { "lbrv", N_("AMD LBR Virtualization support") },
+ { "svm_lock", N_("AMD SVM locking MSR") },
+ { "nrip_save", N_("AMD SVM next_rip save") },
+ { "tsc_scale", N_("AMD TSC scaling support") },
+ { "vmcb_clean", N_("AMD VMCB clean bits support") },
+ { "flushbyasid", N_("AMD flush-by-ASID support") },
+ { "decodeassists", N_("AMD Decode Assists support") },
+ { "pausefilter", N_("AMD filtered pause intercept") },
+ { "pfthreshold", N_("AMD pause filter threshold") },
+ { "avic", N_("Virtual Interrupt Controller") },
/* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx) */
- { "pku", N_("Protection Keys for Userspace") },
- { "ospke", N_("OS Protection Keys Enable") },
+ { "pku", N_("Protection Keys for Userspace") },
+ { "ospke", N_("OS Protection Keys Enable") },
/* AMD-defined CPU features, CPUID level 0x80000007 (ebx) */
- { "overflow_recov", N_("MCA overflow recovery support") },
- { "succor", N_("uncorrectable error containment and recovery") },
- { "smca", N_("Scalable MCA") },
+ { "overflow_recov", N_("MCA overflow recovery support") },
+ { "succor", N_("uncorrectable error containment and recovery") },
+ { "smca", N_("Scalable MCA") },
{ NULL, NULL},
};