arm: more flag definitions

A few more flag definitions for ARM.

Signed-off-by: Burt P <pburt0@gmail.com>

1 files changed, 14 insertions, 3 deletions

diff --git a/modules/devices/arm/processor.c b/modules/devices/arm/processor.c
index 587bb507..890de28a 100644
--- a/modules/devices/arm/processor.c
+++ b/modules/devices/arm/processor.c
@@ -19,10 +19,14 @@
 #include "hardinfo.h"
 #include "devices.h"
 
-/* source: https://unix.stackexchange.com/a/43563 */
+/* sources:
+ *   https://unix.stackexchange.com/a/43563
+ *   git:linux/arch/arm/kernel/setup.c
+ */
 static struct {
     char *name, *meaning;
 } flag_meaning[] = {
+    /* hw_cap */
     { "swp",	"SWP instruction (atomic read-modify-write)" },
     { "half",	"Half-word loads and stores" },
     { "thumb",	"Thumb (16-bit instruction set)" },
@@ -36,7 +40,6 @@ static struct {
     { "crunch",	"MaverickCrunch coprocessor (if kernel support enabled)" },
     { "thumbee",	"ThumbEE" },
     { "neon",	"Advanced SIMD/NEON on AArch32" },
-    { "asimd",	"Advanced SIMD/NEON on AArch64" },
     { "evtstrm",	"kernel event stream using generic architected timer" },
     { "vfpv3",	"VFP version 3" },
     { "vfpv3d16",	"VFP version 3 with 16 D-registers" },
@@ -45,7 +48,15 @@ static struct {
     { "tls",	"TLS register" },
     { "idiva",	"SDIV and UDIV hardware division in ARM mode" },
     { "idivt",	"SDIV and UDIV hardware division in Thumb mode" },
-    { "pmull{2}",	"64x64->128-bit F2m multiplication" },
+    { "lpae",	"40-bit Large Physical Address Extension" },
+    /* hw_cap2 */
+    { "pmull",	"64x64->128-bit F2m multiplication (arch>8)" },
+    { "aes",	"Crypto:AES (arch>8)" },
+    { "sha1",	"Crypto:SHA1 (arch>8)" },
+    { "sha2",	"Crypto:SHA2 (arch>8)" },
+    { "crc32",	"CRC32 checksum instructions (arch>8)" },
+    /* ?? */
+    { "asimd",	"Advanced SIMD/NEON on AArch64 (arch>8)" },
     { NULL, NULL},
 };