x86: update cpuinfo flag meanings

Signed-off-by: Burt P <pburt0@gmail.com>

1 files changed, 228 insertions, 128 deletions

diff --git a/modules/devices/x86/processor.c b/modules/devices/x86/processor.c
index 35ad9fcb..4e0363d4 100644
--- a/modules/devices/x86/processor.c
+++ b/modules/devices/x86/processor.c
@@ -372,139 +372,239 @@ GSList *processor_scan(void)
 
 /*
  * Sources:
- * - Linux' cpufeature.h
- * - http://gentoo-wiki.com/Cpuinfo
+ * - https://unix.stackexchange.com/a/43540
+ * - https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git/tree/arch/x86/include/asm/cpufeatures.h?id=refs/tags/v4.9
  * - Intel IA-32 Architecture Software Development Manual
- * - https://unix.stackexchange.com/questions/43539/what-do-the-flags-in-proc-cpuinfo-mean
+ * - http://gentoo-wiki.com/Cpuinfo
  */
 static struct {
     char *name, *meaning;
 } flag_meaning[] = {
-	{ "3dnow",	"3DNow! Technology"				},
-	{ "3dnowext",	"Extended 3DNow! Technology"			},
-	{ "fpu",	"Floating Point Unit"				},
-	{ "vme",	"Virtual 86 Mode Extension"			},
-	{ "de",		"Debug Extensions - I/O breakpoints"		},
-	{ "pse",	"Page Size Extensions (4MB pages)"		},
-	{ "tsc",	"Time Stamp Counter and RDTSC instruction"	},
-	{ "msr",	"Model Specific Registers"			},
-	{ "pae",	"Physical Address Extensions"			},
-	{ "mce",	"Machine Check Architecture"			},
-	{ "cx8",	"CMPXCHG8 instruction"				},
-	{ "apic",	"Advanced Programmable Interrupt Controller"	},
-	{ "sep",	"Fast System Call (SYSENTER/SYSEXIT)"		},
-	{ "mtrr",	"Memory Type Range Registers"			},
-	{ "pge",	"Page Global Enable"				},
-	{ "mca",	"Machine Check Architecture"			},
-	{ "cmov",	"Conditional Move instruction"			},
-	{ "pat",	"Page Attribute Table"				},
-	{ "pse36",	"36bit Page Size Extensions"			},
-	{ "psn",	"96 bit Processor Serial Number"		},
-	{ "mmx",	"MMX technology"				},
-	{ "mmxext",	"Extended MMX Technology"			},
-	{ "cflush",	"Cache Flush"					},
-	{ "dtes",	"Debug Trace Store"				},
-	{ "fxsr",	"FXSAVE and FXRSTOR instructions"		},
-	{ "kni",	"Streaming SIMD instructions"			},
-	{ "xmm",	"Streaming SIMD instructions"			},
-	{ "ht",		"HyperThreading"				},
-	{ "mp",		"Multiprocessing Capable"			},
-	{ "sse",	"SSE instructions"				},
-	{ "sse2",	"SSE2 (WNI) instructions"			},
-	{ "acc",	"Automatic Clock Control"			},
-	{ "ia64",	"IA64 Instructions"				},
-	{ "syscall",	"SYSCALL and SYSEXIT instructions"		},
-	{ "nx",		"No-execute Page Protection"			},
-	{ "xd",		"Execute Disable"				},
-	{ "clflush",	"Cache Line Flush instruction"			},
-	{ "acpi",	"Thermal Monitor and Software Controlled Clock"	},
-	{ "dts",	"Debug Store"					},
-	{ "ss",		"Self Snoop"					},
-	{ "tm",		"Thermal Monitor"				},
-	{ "pbe",	"Pending Break Enable"				},
-	{ "pb",		"Pending Break Enable"				},
-	{ "pn",		"Processor serial number"			},
-	{ "ds",		"Debug Store"					},
-	{ "xmm2",	"Streaming SIMD Extensions-2"			},
-	{ "xmm3",	"Streaming SIMD Extensions-3"			},
-	{ "selfsnoop",	"CPU self snoop"				},
-	{ "rdtscp",	"RDTSCP"					},
-	{ "recovery",	"CPU in recovery mode"				},
-	{ "longrun",	"Longrun power control"				},
-	{ "lrti",	"LongRun table interface"			},
-	{ "cxmmx",	"Cyrix MMX extensions"				},
-	{ "k6_mtrr",	"AMD K6 nonstandard MTRRs"			},
-	{ "cyrix_arr",	"Cyrix ARRs (= MTRRs)"				},
-	{ "centaur_mcr","Centaur MCRs (= MTRRs)"			},
-	{ "constant_tsc","TSC ticks at a constant rate"			},
-	{ "up",		"smp kernel running on up"			},
-	{ "fxsave_leak","FXSAVE leaks FOP/FIP/FOP"			},
-	{ "arch_perfmon","Intel Architectural PerfMon"			},
-	{ "pebs",	"Precise-Event Based Sampling"			},
-	{ "bts",	"Branch Trace Store"				},
-	{ "sync_rdtsc",	"RDTSC synchronizes the CPU"			},
-	{ "rep_good",	"rep microcode works well on this CPU"		},
-	{ "mwait",	"Monitor/Mwait support"				},
-	{ "ds_cpl",	"CPL Qualified Debug Store"			},
-	{ "est",	"Enhanced SpeedStep"				},
-	{ "tm2",	"Thermal Monitor 2"				},
-	{ "cid",	"Context ID"					},
-	{ "xtpr",	"Send Task Priority Messages"			},
-	{ "xstore",	"on-CPU RNG present (xstore insn)"		},
-	{ "xstore_en",	"on-CPU RNG enabled"				},
-	{ "xcrypt",	"on-CPU crypto (xcrypt insn)"			},
-	{ "xcrypt_en",	"on-CPU crypto enabled"				},
-	{ "ace2",	"Advanced Cryptography Engine v2"		},
-	{ "ace2_en",	"ACE v2 enabled"				},
-	{ "phe",	"PadLock Hash Engine"				},
-	{ "phe_en",	"PHE enabled"					},
-	{ "pmm",	"PadLock Montgomery Multiplier"			},
-	{ "pmm_en",	"PMM enabled"					},
-	{ "lahf_lm",	"LAHF/SAHF in long mode"			},
-	{ "cmp_legacy",	"HyperThreading not valid"			},
-	{ "lm",		"LAHF/SAHF in long mode"			},
-	{ "ds_cpl",	"CPL Qualified Debug Store"			},
-	{ "vmx",	"Virtualization support (Intel)"		},
-	{ "svm",	"Virtualization support (AMD)"			},
-	{ "est",	"Enhanced SpeedStep"				},
-	{ "tm2",	"Thermal Monitor 2"				},
-	{ "ssse3",	"Supplemental Streaming SIMD Extension 3"	},
-	{ "cx16",	"CMPXCHG16B instruction"			},
-	{ "xptr",	"Send Task Priority Messages"			},
-	{ "pebs",	"Precise Event Based Sampling"			},
-	{ "bts",	"Branch Trace Store"				},
-	{ "ida",	"Intel Dynamic Acceleration"			},
-	{ "arch_perfmon","Intel Architectural PerfMon"			},
-	{ "pni",	"Streaming SIMD Extension 3 (Prescott New Instruction)"	},
-	{ "rep_good",	"rep microcode works well on this CPU"		},
-	{ "ts",		"Thermal Sensor"				},
-	{ "sse3",	"Streaming SIMD Extension 3"			},
-	{ "sse4",	"Streaming SIMD Extension 4"			},
-	{ "tni",	"Tejas New Instruction"				},
-	{ "nni",	"Nehalem New Instruction"			},
-	{ "tpr",	"Task Priority Register"			},
-	{ "vid",	"Voltage Identifier"				},
-	{ "fid", 	"Frequency Identifier"				},
-	{ "dtes64", 	"64-bit Debug Store"				},
-	{ "monitor", 	"Monitor/Mwait support"				},
-	{ "sse4_1",     "Streaming SIMD Extension 4.1"                  },
-	{ "sse4_2",     "Streaming SIMD Extension 4.2"                  },
-	{ "nopl",       "NOPL instructions"                             },
-	{ "cxmmx",      "Cyrix MMX extensions"                          },
-	{ "xtopology",  "CPU topology enum extensions"                  },
-	{ "nonstop_tsc", "TSC does not stop in C states"                },
-	{ "eagerfpu",   "Non lazy FPU restor"                           },
-	{ "pclmulqdq",  "Perform a Carry-Less Multiplication of Quadword instruction" },
-	{ "smx",        "Safer mode: TXT (TPM support)"                 },
-	{ "pdcm",       "Performance capabilities"                      },
-	{ "pcid",       "Process Context Identifiers"                   },
-	{ "x2apic",     "x2APIC"                                        },
-	{ "popcnt",     "Set bit count instructions"                    },
-	{ "aes",        "Advanced Encryption Standard"                  },
-	{ "aes-ni",     "Advanced Encryption Standard (New Instructions)" },
-	{ "xsave",      "Save Processor Extended States"                },
-	{ "avx",        "Advanced Vector Instructions"                  },
-	{ NULL,		NULL						},
+/* Intel-defined CPU features, CPUID level 0x00000001 (edx)
+ * See also Wikipedia and table 2-27 in Intel Advanced Vector Extensions Programming Reference */
+    { "fpu",	 "Onboard FPU (floating point support)" },
+    { "vme",	 "Virtual 8086 mode enhancements" },
+    { "de", 	 "Debugging Extensions (CR4.DE)" },
+    { "pse",	 "Page Size Extensions (4MB memory pages)" },
+    { "tsc",	 "Time Stamp Counter (RDTSC)" },
+    { "msr",	 "Model-Specific Registers (RDMSR, WRMSR)" },
+    { "pae",	 "Physical Address Extensions (support for more than 4GB of RAM)" },
+    { "mce",	 "Machine Check Exception" },
+    { "cx8",	 "CMPXCHG8 instruction (64-bit compare-and-swap)" },
+    { "apic",	 "Onboard APIC" },
+    { "sep",	 "SYSENTER/SYSEXIT" },
+    { "mtrr",	 "Memory Type Range Registers" },
+    { "pge",	 "Page Global Enable (global bit in PDEs and PTEs)" },
+    { "mca",	 "Machine Check Architecture" },
+    { "cmov",	 "CMOV instructions (conditional move) (also FCMOV)" },
+    { "pat",	 "Page Attribute Table" },
+    { "pse36",	 "36-bit PSEs (huge pages)" },
+    { "pn", 	 "Processor serial number" },
+    { "clflush",	 "Cache Line Flush instruction" },
+    { "dts",	 "Debug Store (buffer for debugging and profiling instructions)" },
+    { "acpi",	 "ACPI via MSR (temperature monitoring and clock speed modulation)" },
+    { "mmx",	 "Multimedia Extensions" },
+    { "fxsr",	 "FXSAVE/FXRSTOR, CR4.OSFXSR" },
+    { "sse",	 "Intel SSE vector instructions" },
+    { "sse2",	 "SSE2" },
+    { "ss", 	 "CPU self snoop" },
+    { "ht", 	 "Hyper-Threading" },
+    { "tm", 	 "Automatic clock control (Thermal Monitor)" },
+    { "ia64",	 "Intel Itanium Architecture 64-bit (not to be confused with Intel's 64-bit x86 architecture with flag x86-64 or \"AMD64\" bit indicated by flag lm)" },
+    { "pbe",	 "Pending Break Enable (PBE# pin) wakeup support" },
+/* AMD-defined CPU features, CPUID level 0x80000001
+ * See also Wikipedia and table 2-23 in Intel Advanced Vector Extensions Programming Reference */
+    { "syscall",	 "SYSCALL (Fast System Call) and SYSRET (Return From Fast System Call)" },
+    { "mp", 	 "Multiprocessing Capable." },
+    { "nx", 	 "Execute Disable" },
+    { "mmxext",	 "AMD MMX extensions" },
+    { "fxsr_opt",	 "FXSAVE/FXRSTOR optimizations" },
+    { "pdpe1gb",	 "One GB pages (allows hugepagesz=1G)" },
+    { "rdtscp",	 "Read Time-Stamp Counter and Processor ID" },
+    { "lm", 	 "Long Mode (x86-64: amd64, also known as Intel 64, i.e. 64-bit capable)" },
+    { "3dnow",	 "3DNow! (AMD vector instructions, competing with Intel's SSE1)" },
+    { "3dnowext",	 "AMD 3DNow! extensions" },
+/* Transmeta-defined CPU features, CPUID level 0x80860001 */
+    { "recovery",	 "CPU in recovery mode" },
+    { "longrun",	 "Longrun power control" },
+    { "lrti",	 "LongRun table interface" },
+/* Other features, Linux-defined mapping */
+    { "cxmmx",	 "Cyrix MMX extensions" },
+    { "k6_mtrr",	 "AMD K6 nonstandard MTRRs" },
+    { "cyrix_arr",	 "Cyrix ARRs (= MTRRs)" },
+    { "centaur_mcr",	 "Centaur MCRs (= MTRRs)" },
+    { "constant_tsc",	 "TSC ticks at a constant rate" },
+    { "up", 	 "SMP kernel running on UP" },
+    { "art",	 "Always-Running Timer" },
+    { "arch_perfmon",	 "Intel Architectural PerfMon" },
+    { "pebs",	 "Precise-Event Based Sampling" },
+    { "bts",	 "Branch Trace Store" },
+    { "rep_good",	 "rep microcode works well" },
+    { "acc_power",	 "AMD accumulated power mechanism" },
+    { "nopl",	 "The NOPL (0F 1F) instructions" },
+    { "xtopology",	 "cpu topology enum extensions" },
+    { "tsc_reliable",	 "TSC is known to be reliable" },
+    { "nonstop_tsc",	 "TSC does not stop in C states" },
+    { "extd_apicid",	 "has extended APICID (8 bits)" },
+    { "amd_dcm",	 "multi-node processor" },
+    { "aperfmperf",	 "APERFMPERF" },
+    { "eagerfpu",	 "Non lazy FPU restore" },
+    { "nonstop_tsc_s3",	 "TSC doesn't stop in S3 state" },
+    { "mce_recovery",	 "CPU has recoverable machine checks" },
+/* Intel-defined CPU features, CPUID level 0x00000001 (ecx)
+ * See also Wikipedia and table 2-26 in Intel Advanced Vector Extensions Programming Reference */
+    { "pni",	 "SSE-3 (“Prescott New Instructions”)" },
+    { "pclmulqdq",	 "Perform a Carry-Less Multiplication of Quadword instruction — accelerator for GCM)" },
+    { "dtes64",	 "64-bit Debug Store" },
+    { "monitor",	 "Monitor/Mwait support (Intel SSE3 supplements)" },
+    { "ds_cpl",	 "CPL Qual. Debug Store" },
+    { "vmx: Hardware virtualization",	 "Intel VMX" },
+    { "smx: Safer mode",	 "TXT (TPM support)" },
+    { "est",	 "Enhanced SpeedStep" },
+    { "tm2",	 "Thermal Monitor 2" },
+    { "ssse3",	 "Supplemental SSE-3" },
+    { "cid",	 "Context ID" },
+    { "sdbg",	 "silicon debug" },
+    { "fma",	 "Fused multiply-add" },
+    { "cx16",	 "CMPXCHG16B" },
+    { "xtpr",	 "Send Task Priority Messages" },
+    { "pdcm",	 "Performance Capabilities" },
+    { "pcid",	 "Process Context Identifiers" },
+    { "dca",	 "Direct Cache Access" },
+    { "sse4_1",	 "SSE-4.1" },
+    { "sse4_2",	 "SSE-4.2" },
+    { "x2apic",	 "x2APIC" },
+    { "movbe",	 "Move Data After Swapping Bytes instruction" },
+    { "popcnt",	 "Return the Count of Number of Bits Set to 1 instruction (Hamming weight, i.e. bit count)" },
+    { "tsc_deadline_timer",	 "Tsc deadline timer" },
+    { "aes/aes-ni",	 "Advanced Encryption Standard (New Instructions)" },
+    { "xsave",	 "Save Processor Extended States: also provides XGETBY,XRSTOR,XSETBY" },
+    { "avx",	 "Advanced Vector Extensions" },
+    { "f16c",	 "16-bit fp conversions (CVT16)" },
+    { "rdrand",	 "Read Random Number from hardware random number generator instruction" },
+    { "hypervisor",	 "Running on a hypervisor" },
+/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001 */
+    { "rng",	 "Random Number Generator present (xstore)" },
+    { "rng_en",	 "Random Number Generator enabled" },
+    { "ace",	 "on-CPU crypto (xcrypt)" },
+    { "ace_en",	 "on-CPU crypto enabled" },
+    { "ace2",	 "Advanced Cryptography Engine v2" },
+    { "ace2_en",	 "ACE v2 enabled" },
+    { "phe",	 "PadLock Hash Engine" },
+    { "phe_en",	 "PHE enabled" },
+    { "pmm",	 "PadLock Montgomery Multiplier" },
+    { "pmm_en",	 "PMM enabled" },
+/* More extended AMD flags: CPUID level 0x80000001, ecx */
+    { "lahf_lm",	 "Load AH from Flags (LAHF) and Store AH into Flags (SAHF) in long mode" },
+    { "cmp_legacy",	 "If yes HyperThreading not valid" },
+    { "svm",	 "\"Secure virtual machine\": AMD-V" },
+    { "extapic",	 "Extended APIC space" },
+    { "cr8_legacy",	 "CR8 in 32-bit mode" },
+    { "abm",	 "Advanced Bit Manipulation" },
+    { "sse4a",	 "SSE-4A" },
+    { "misalignsse",	 "indicates if a general-protection exception (#GP) is generated when some legacy SSE instructions operate on unaligned data. Also depends on CR0 and Alignment Checking bit" },
+    { "3dnowprefetch",	 "3DNow prefetch instructions" },
+    { "osvw",	 "indicates OS Visible Workaround, which allows the OS to work around processor errata." },
+    { "ibs",	 "Instruction Based Sampling" },
+    { "xop",	 "extended AVX instructions" },
+    { "skinit",	 "SKINIT/STGI instructions" },
+    { "wdt",	 "Watchdog timer" },
+    { "lwp",	 "Light Weight Profiling" },
+    { "fma4",	 "4 operands MAC instructions" },
+    { "tce",	 "translation cache extension" },
+    { "nodeid_msr",	 "NodeId MSR" },
+    { "tbm",	 "Trailing Bit Manipulation" },
+    { "topoext",	 "Topology Extensions CPUID leafs" },
+    { "perfctr_core",	 "Core Performance Counter Extensions" },
+    { "perfctr_nb",	 "NB Performance Counter Extensions" },
+    { "bpext",	 "data breakpoint extension" },
+    { "ptsc",	 "performance time-stamp counter" },
+    { "perfctr_l2",	 "L2 Performance Counter Extensions" },
+    { "mwaitx",	 "MWAIT extension (MONITORX/MWAITX)" },
+/* Auxiliary flags: Linux defined - For features scattered in various CPUID levels */
+    { "cpb",	 "AMD Core Performance Boost" },
+    { "epb",	 "IA32_ENERGY_PERF_BIAS support" },
+    { "hw_pstate",	 "AMD HW-PState" },
+    { "proc_feedback",	 "AMD ProcFeedbackInterface" },
+    { "intel_pt",	 "Intel Processor Tracing" },
+/* Virtualization flags: Linux defined */
+    { "tpr_shadow",	 "Intel TPR Shadow" },
+    { "vnmi",	 "Intel Virtual NMI" },
+    { "flexpriority",	 "Intel FlexPriority" },
+    { "ept",	 "Intel Extended Page Table" },
+    { "vpid",	 "Intel Virtual Processor ID" },
+    { "vmmcall",	 "prefer VMMCALL to VMCALL" },
+/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx) */
+    { "fsgsbase",	 "{RD/WR}{FS/GS}BASE instructions" },
+    { "tsc_adjust",	 "TSC adjustment MSR" },
+    { "bmi1",	 "1st group bit manipulation extensions" },
+    { "hle",	 "Hardware Lock Elision" },
+    { "avx2",	 "AVX2 instructions" },
+    { "smep",	 "Supervisor Mode Execution Protection" },
+    { "bmi2",	 "2nd group bit manipulation extensions" },
+    { "erms",	 "Enhanced REP MOVSB/STOSB" },
+    { "invpcid",	 "Invalidate Processor Context ID" },
+    { "rtm",	 "Restricted Transactional Memory" },
+    { "cqm",	 "Cache QoS Monitoring" },
+    { "mpx",	 "Memory Protection Extension" },
+    { "avx512f",	 "AVX-512 foundation" },
+    { "avx512dq",	 "AVX-512 Double/Quad instructions" },
+    { "rdseed",	 "The RDSEED instruction" },
+    { "adx",	 "The ADCX and ADOX instructions" },
+    { "smap",	 "Supervisor Mode Access Prevention" },
+    { "clflushopt",	 "CLFLUSHOPT instruction" },
+    { "clwb",	 "CLWB instruction" },
+    { "avx512pf",	 "AVX-512 Prefetch" },
+    { "avx512er",	 "AVX-512 Exponential and Reciprocal" },
+    { "avx512cd",	 "AVX-512 Conflict Detection" },
+    { "sha_ni",	 "SHA1/SHA256 Instruction Extensions" },
+    { "avx512bw",	 "AVX-512 Byte/Word instructions" },
+    { "avx512vl",	 "AVX-512 128/256 Vector Length extensions" },
+/* Extended state features, CPUID level 0x0000000d:1 (eax) */
+    { "xsaveopt",	 "Optimized XSAVE" },
+    { "xsavec",	 "XSAVEC" },
+    { "xgetbv1",	 "XGETBV with ECX = 1" },
+    { "xsaves",	 "XSAVES/XRSTORS" },
+/* Intel-defined CPU QoS sub-leaf, CPUID level 0x0000000F:0 (edx) */
+    { "cqm_llc",	 "LLC QoS" },
+/* Intel-defined CPU QoS sub-leaf, CPUID level 0x0000000F:1 (edx) */
+    { "cqm_occup_llc",	 "LLC occupancy monitoring" },
+    { "cqm_mbm_total",	 "LLC total MBM monitoring" },
+    { "cqm_mbm_local",	 "LLC local MBM monitoring" },
+/* AMD-defined CPU features, CPUID level 0x80000008 (ebx) */
+    { "clzero",	 "CLZERO instruction" },
+    { "irperf",	 "instructions retired performance counter" },
+/* Thermal and Power Management leaf, CPUID level 0x00000006 (eax) */
+    { "dtherm (formerly dts)",	 "digital thermal sensor" },
+    { "ida",	 "Intel Dynamic Acceleration" },
+    { "arat",	 "Always Running APIC Timer" },
+    { "pln",	 "Intel Power Limit Notification" },
+    { "pts",	 "Intel Package Thermal Status" },
+    { "hwp",	 "Intel Hardware P-states" },
+    { "hwp_notify",	 "HWP notification" },
+    { "hwp_act_window",	 "HWP Activity Window" },
+    { "hwp_epp",	 "HWP Energy Performance Preference" },
+    { "hwp_pkg_req",	 "HWP package-level request" },
+/* AMD SVM Feature Identification, CPUID level 0x8000000a (edx) */
+    { "npt",	 "AMD Nested Page Table support" },
+    { "lbrv",	 "AMD LBR Virtualization support" },
+    { "svm_lock",	 "AMD SVM locking MSR" },
+    { "nrip_save",	 "AMD SVM next_rip save" },
+    { "tsc_scale",	 "AMD TSC scaling support" },
+    { "vmcb_clean",	 "AMD VMCB clean bits support" },
+    { "flushbyasid",	 "AMD flush-by-ASID support" },
+    { "decodeassists",	 "AMD Decode Assists support" },
+    { "pausefilter",	 "AMD filtered pause intercept" },
+    { "pfthreshold",	 "AMD pause filter threshold" },
+    { "avic",	 "Virtual Interrupt Controller" },
+/* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx) */
+    { "pku",	 "Protection Keys for Userspace" },
+    { "ospke",	 "OS Protection Keys Enable" },
+/* AMD-defined CPU features, CPUID level 0x80000007 (ebx) */
+    { "overflow_recov",	 "MCA overflow recovery support" },
+    { "succor",	 "uncorrectable error containment and recovery" },
+    { "smca",	 "Scalable MCA" },
+    { NULL, NULL},
 };
 
 static struct {