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| author | Simon Quigley <tsimonq2@ubuntu.com> | 2017-08-16 04:32:39 -0500 |
|---|---|---|
| committer | Simon Quigley <tsimonq2@ubuntu.com> | 2017-08-16 04:32:39 -0500 |
| commit | 82306ca849c0710209e5a39754f446d0335a276d (patch) | |
| tree | 8d297400e5c36357b9147401631e653e035283d3 /test/data/mips_loongson_cpuinfo | |
| parent | 21a53faf18b01a65a341115000e97d70b37c750c (diff) | |
| parent | 9a9db98089717990cd5e0eef529f6bb0819ebe46 (diff) | |
Updated version 0.5.1+git20170815 from 'upstream/0.5.1+git20170815'
with Debian dir 36bf8e7e43d9f6621a63c79a597af2f4f76271b7
Diffstat (limited to 'test/data/mips_loongson_cpuinfo')
| -rw-r--r-- | test/data/mips_loongson_cpuinfo | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/test/data/mips_loongson_cpuinfo b/test/data/mips_loongson_cpuinfo new file mode 100644 index 00000000..f2ee0e90 --- /dev/null +++ b/test/data/mips_loongson_cpuinfo @@ -0,0 +1,13 @@ +system type : gdium +processor : 0 +cpu model : ICT Loongson-2 V0.3 FPU V0.1 +BogoMIPS : 598.60 +wait instruction : no +microsecond timers : yes +tlb_entries : 64 +extra interrupt vector : no +hardware watchpoint : no +ASEs implemented : +shadow register sets : 1 +VCED exceptions : not available +VCEI exceptions : not available |