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-rw-r--r--includes/riscv/processor-platform.h1
-rw-r--r--modules/devices/riscv/processor.c38
-rw-r--r--modules/devices/riscv/riscv_data.c105
-rw-r--r--modules/devices/riscv/riscv_data.h27
4 files changed, 169 insertions, 2 deletions
diff --git a/includes/riscv/processor-platform.h b/includes/riscv/processor-platform.h
index f5e4758e..07cbf86e 100644
--- a/includes/riscv/processor-platform.h
+++ b/includes/riscv/processor-platform.h
@@ -29,6 +29,7 @@ struct _Processor {
gchar *model_name;
gchar *mmu, *isa, *uarch;
+ gchar *flags; /* expanded from isa */
gfloat bogomips; /* not used */
};
diff --git a/modules/devices/riscv/processor.c b/modules/devices/riscv/processor.c
index b27a2c10..92d5c474 100644
--- a/modules/devices/riscv/processor.c
+++ b/modules/devices/riscv/processor.c
@@ -22,6 +22,9 @@
#include "devices.h"
#include "cpu_util.h"
+#include "riscv_data.h"
+#include "riscv_data.c"
+
GSList *
processor_scan(void)
{
@@ -122,6 +125,8 @@ processor_scan(void)
UNKIFNULL(isa);
UNKIFNULL(uarch);
+ processor->flags = riscv_isa_to_flags(processor->isa);
+
/* topo & freq */
processor->cpufreq = cpufreq_new(processor->id);
processor->cputopo = cputopo_new(processor->id);
@@ -135,12 +140,37 @@ processor_scan(void)
return procs;
}
+gchar *processor_get_capabilities_from_flags(gchar * strflags)
+{
+ gchar **flags, **old;
+ gchar *tmp = NULL;
+ gint j = 0;
+
+ flags = g_strsplit(strflags, " ", 0);
+ old = flags;
+
+ while (flags[j]) {
+ const gchar *meaning = riscv_ext_meaning( flags[j] );
+
+ if (meaning) {
+ tmp = h_strdup_cprintf("%s=%s\n", tmp, flags[j], meaning);
+ } else {
+ tmp = h_strdup_cprintf("%s=\n", tmp, flags[j]);
+ }
+ j++;
+ }
+ if (tmp == NULL || g_strcmp0(tmp, "") == 0)
+ tmp = g_strdup_printf("%s=%s\n", "empty", _("Empty List"));
+
+ g_strfreev(old);
+ return tmp;
+}
gchar *
processor_get_detailed_info(Processor *processor)
{
- gchar *tmp_cpufreq, *tmp_topology, *ret;
-
+ gchar *tmp_flags, *tmp_cpufreq, *tmp_topology, *ret;
+ tmp_flags = processor_get_capabilities_from_flags(processor->flags);
tmp_topology = cputopo_section_str(processor->cputopo);
tmp_cpufreq = cpufreq_section_str(processor->cpufreq);
@@ -153,6 +183,8 @@ processor_get_detailed_info(Processor *processor)
"%s=%s\n" /* byte order */
"%s" /* topology */
"%s" /* frequency scaling */
+ "[%s]\n" /* extensions */
+ "%s"
"%s",/* empty */
_("Processor"),
_("Model"), processor->model_name,
@@ -163,7 +195,9 @@ processor_get_detailed_info(Processor *processor)
_("Byte Order"), byte_order_str(),
tmp_topology,
tmp_cpufreq,
+ _("Capabilities"), tmp_flags,
"");
+ g_free(tmp_flags);
g_free(tmp_cpufreq);
g_free(tmp_topology);
return ret;
diff --git a/modules/devices/riscv/riscv_data.c b/modules/devices/riscv/riscv_data.c
new file mode 100644
index 00000000..77cb69ca
--- /dev/null
+++ b/modules/devices/riscv/riscv_data.c
@@ -0,0 +1,105 @@
+/*
+ * rpiz - https://github.com/bp0/rpiz
+ * Copyright (C) 2017 Burt P. <pburt0@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include "riscv_data.h"
+
+static struct {
+ char *name, *meaning;
+} tab_ext_meaning[] = {
+ { "rv32", "32-bit" },
+ { "rv64", "64-bit" },
+ { "rv128", "128-bit" },
+ { "rv_E", "Base embedded integer instructions (15 registers)" },
+ { "rv_I", "Base integer instructions (31 registers)" },
+ { "rv_M", "Hardware integer multiply and divide" },
+ { "rv_A", "Atomic memory operations" },
+ { "rv_C", "Compressed 16-bit instructions" },
+ { "rv_F", "Floating-point instructions, single-precision" },
+ { "rv_D", "Floating-point instructions, double-precision" },
+ { "rv_Q", "Floating-point instructions, quad-precision" },
+ { "rv_B", "Bit manipulation instructions" },
+ { "rv_V", "Vector operations" },
+ { "rv_T", "Transactional memory" },
+ { "rv_P", "Packed SIMD instructions" },
+ { "rv_L", "Decimal floating-point instructions" },
+ { NULL, NULL }
+};
+
+const char *riscv_ext_meaning(const char *ext) {
+ int i = 0;
+ if (ext)
+ while(tab_ext_meaning[i].name != NULL) {
+ if (strcmp(tab_ext_meaning[i].name, ext) == 0)
+ return tab_ext_meaning[i].meaning;
+ i++;
+ }
+ return NULL;
+}
+
+#define FSTR_SIZE 1024
+#define ADD_EXT_FLAG(ext) l = strlen(ext); strncpy(pd, ext " ", l + 1); pd += l + 1;
+char *riscv_isa_to_flags(const char *isa) {
+ char *flags = NULL, *ps = (char*)isa, *pd = NULL;
+ int l = 0;
+ if (isa) {
+ flags = malloc(FSTR_SIZE);
+ if (flags) {
+ memset(flags, 0, FSTR_SIZE);
+ pd = flags;
+ if ( strncmp(ps, "RV32", 4) == 0 ) {
+ ADD_EXT_FLAG("rv32");
+ ps += 4;
+ } else if ( strncmp(ps, "RV64", 4) == 0 ) {
+ ADD_EXT_FLAG("rv64");
+ ps += 4;
+ } else if ( strncmp(ps, "RV128", 5) == 0) {
+ ADD_EXT_FLAG("rv128");
+ ps += 5;
+ }
+ while (*ps != 0) {
+ switch(*ps) {
+ case 'G': /* G = IMAFD */
+ ADD_EXT_FLAG("rv_I");
+ ADD_EXT_FLAG("rv_M");
+ ADD_EXT_FLAG("rv_A");
+ ADD_EXT_FLAG("rv_F");
+ ADD_EXT_FLAG("rv_D");
+ break;
+ case 'E': ADD_EXT_FLAG("rv_E"); break;
+ case 'I': ADD_EXT_FLAG("rv_I"); break;
+ case 'M': ADD_EXT_FLAG("rv_M"); break;
+ case 'A': ADD_EXT_FLAG("rv_A"); break;
+ case 'C': ADD_EXT_FLAG("rv_C"); break;
+ case 'F': ADD_EXT_FLAG("rv_F"); break;
+ case 'D': ADD_EXT_FLAG("rv_D"); break;
+ case 'Q': ADD_EXT_FLAG("rv_Q"); break;
+ case 'B': ADD_EXT_FLAG("rv_B"); break;
+ case 'V': ADD_EXT_FLAG("rv_V"); break;
+ default: break;
+ }
+ ps++;
+ }
+ }
+ }
+ return flags;
+}
diff --git a/modules/devices/riscv/riscv_data.h b/modules/devices/riscv/riscv_data.h
new file mode 100644
index 00000000..aa5a9480
--- /dev/null
+++ b/modules/devices/riscv/riscv_data.h
@@ -0,0 +1,27 @@
+/*
+ * rpiz - https://github.com/bp0/rpiz
+ * Copyright (C) 2017 Burt P. <pburt0@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+
+#ifndef _RISCVDATA_H_
+#define _RISCVDATA_H_
+
+char *riscv_isa_to_flags(const char *isa);
+const char *riscv_ext_meaning(const char *ext);
+
+#endif
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