diff options
Diffstat (limited to 'modules/devices/arm/arm_data.c')
| -rw-r--r-- | modules/devices/arm/arm_data.c | 95 |
1 files changed, 53 insertions, 42 deletions
diff --git a/modules/devices/arm/arm_data.c b/modules/devices/arm/arm_data.c index 2e2cbe60..60e8ea34 100644 --- a/modules/devices/arm/arm_data.c +++ b/modules/devices/arm/arm_data.c @@ -23,6 +23,13 @@ #include <string.h> #include "arm_data.h" +#ifndef C_ +#define C_(Ctx, String) String +#endif +#ifndef NC_ +#define NC_(Ctx, String) String +#endif + /* sources: * https://unix.stackexchange.com/a/43563 * git:linux/arch/arm/kernel/setup.c @@ -32,47 +39,46 @@ static struct { char *name, *meaning; } tab_flag_meaning[] = { /* arm/hw_cap */ - { "swp", "SWP instruction (atomic read-modify-write)" }, - { "half", "Half-word loads and stores" }, - { "thumb", "Thumb (16-bit instruction set)" }, - { "26bit", "26-Bit Model (Processor status register folded into program counter)" }, - { "fastmult", "32x32->64-bit multiplication" }, - { "fpa", "Floating point accelerator" }, - { "vfp", "VFP (early SIMD vector floating point instructions)" }, - { "edsp", "DSP extensions (the 'e' variant of the ARM9 CPUs, and all others above)" }, - { "java", "Jazelle (Java bytecode accelerator)" }, - { "iwmmxt", "SIMD instructions similar to Intel MMX" }, - { "crunch", "MaverickCrunch coprocessor (if kernel support enabled)" }, - { "thumbee", "ThumbEE" }, - { "neon", "Advanced SIMD/NEON on AArch32" }, - { "evtstrm", "kernel event stream using generic architected timer" }, - { "vfpv3", "VFP version 3" }, - { "vfpv3d16", "VFP version 3 with 16 D-registers" }, - { "vfpv4", "VFP version 4 with fast context switching" }, - { "vfpd32", "VFP with 32 D-registers" }, - { "tls", "TLS register" }, - { "idiva", "SDIV and UDIV hardware division in ARM mode" }, - { "idivt", "SDIV and UDIV hardware division in Thumb mode" }, - { "lpae", "40-bit Large Physical Address Extension" }, + { "swp", NC_("arm-flag", /*/flag:swp*/ "SWP instruction (atomic read-modify-write)") }, + { "half", NC_("arm-flag", /*/flag:half*/ "Half-word loads and stores") }, + { "thumb", NC_("arm-flag", /*/flag:thumb*/ "Thumb (16-bit instruction set)") }, + { "26bit", NC_("arm-flag", /*/flag:26bit*/ "26-Bit Model (Processor status register folded into program counter)") }, + { "fastmult", NC_("arm-flag", /*/flag:fastmult*/ "32x32->64-bit multiplication") }, + { "fpa", NC_("arm-flag", /*/flag:fpa*/ "Floating point accelerator") }, + { "vfp", NC_("arm-flag", /*/flag:vfp*/ "VFP (early SIMD vector floating point instructions)") }, + { "edsp", NC_("arm-flag", /*/flag:edsp*/ "DSP extensions (the 'e' variant of the ARM9 CPUs, and all others above)") }, + { "java", NC_("arm-flag", /*/flag:java*/ "Jazelle (Java bytecode accelerator)") }, + { "iwmmxt", NC_("arm-flag", /*/flag:iwmmxt*/ "SIMD instructions similar to Intel MMX") }, + { "crunch", NC_("arm-flag", /*/flag:crunch*/ "MaverickCrunch coprocessor (if kernel support enabled)") }, + { "thumbee", NC_("arm-flag", /*/flag:thumbee*/ "ThumbEE") }, + { "neon", NC_("arm-flag", /*/flag:neon*/ "Advanced SIMD/NEON on AArch32") }, + { "evtstrm", NC_("arm-flag", /*/flag:evtstrm*/ "Kernel event stream using generic architected timer") }, + { "vfpv3", NC_("arm-flag", /*/flag:vfpv3*/ "VFP version 3") }, + { "vfpv3d16", NC_("arm-flag", /*/flag:vfpv3d16*/ "VFP version 3 with 16 D-registers") }, + { "vfpv4", NC_("arm-flag", /*/flag:vfpv4*/ "VFP version 4 with fast context switching") }, + { "vfpd32", NC_("arm-flag", /*/flag:vfpd32*/ "VFP with 32 D-registers") }, + { "tls", NC_("arm-flag", /*/flag:tls*/ "TLS register") }, + { "idiva", NC_("arm-flag", /*/flag:idiva*/ "SDIV and UDIV hardware division in ARM mode") }, + { "idivt", NC_("arm-flag", /*/flag:idivt*/ "SDIV and UDIV hardware division in Thumb mode") }, + { "lpae", NC_("arm-flag", /*/flag:lpae*/ "40-bit Large Physical Address Extension") }, /* arm/hw_cap2 */ - { "pmull", "64x64->128-bit F2m multiplication (arch>8)" }, - { "aes", "Crypto:AES (arch>8)" }, - { "sha1", "Crypto:SHA1 (arch>8)" }, - { "sha2", "Crypto:SHA2 (arch>8)" }, - { "crc32", "CRC32 checksum instructions (arch>8)" }, + { "pmull", NC_("arm-flag", /*/flag:pmull*/ "64x64->128-bit F2m multiplication (arch>8)") }, + { "aes", NC_("arm-flag", /*/flag:aes*/ "Crypto:AES (arch>8)") }, + { "sha1", NC_("arm-flag", /*/flag:sha1*/ "Crypto:SHA1 (arch>8)") }, + { "sha2", NC_("arm-flag", /*/flag:sha2*/ "Crypto:SHA2 (arch>8)") }, + { "crc32", NC_("arm-flag", /*/flag:crc32*/ "CRC32 checksum instructions (arch>8)") }, /* arm64/hw_cap */ - { "fp", "" }, - { "asimd", "Advanced SIMD/NEON on AArch64 (arch>8)" }, - { "atomics", "" }, - { "fphp", "" }, - { "asimdhp", "" }, - { "cpuid", "" }, - { "asimdrdm", "" }, - { "jscvt", "" }, - { "fcma", "" }, - { "lrcpc", "" }, - - { NULL, NULL}, + { "fp", NULL }, + { "asimd", NC_("arm-flag", /*/flag:asimd*/ "Advanced SIMD/NEON on AArch64 (arch>8)") }, + { "atomics", NULL }, + { "fphp", NULL }, + { "asimdhp", NULL }, + { "cpuid", NULL }, + { "asimdrdm", NULL }, + { "jscvt", NULL }, + { "fcma", NULL }, + { "lrcpc", NULL }, + { NULL, NULL } }; static struct { @@ -108,9 +114,11 @@ static struct { /*d */ { 0xd01, "Cortex-A32" }, /*dt*/ { 0xd03, "Cortex-A53" }, /*d */ { 0xd04, "Cortex-A35" }, + /*d */ { 0xd05, "Cortex-A55" }, /*d */ { 0xd07, "Cortex-A57 MPCore" }, /*d */ { 0xd08, "Cortex-A72" }, /*d */ { 0xd09, "Cortex-A73" }, + /*d */ { 0xd0a, "Cortex-A75" }, { 0, NULL}, }; @@ -143,8 +151,11 @@ const char *arm_flag_meaning(const char *flag) { int i = 0; if (flag) while(tab_flag_meaning[i].name != NULL) { - if (strcmp(tab_flag_meaning[i].name, flag) == 0) - return tab_flag_meaning[i].meaning; + if (strcmp(tab_flag_meaning[i].name, flag) == 0) { + if (tab_flag_meaning[i].meaning != NULL) + return C_("arm-flag", tab_flag_meaning[i].meaning); + else return NULL; + } i++; } return NULL; @@ -220,7 +231,7 @@ char *arm_decoded_name(const char *imp, const char *part, const char *var, const p = strtol(rev, NULL, 0); imp_name = (char*) arm_implementer(imp); part_desc = (char*) arm_part(imp, part); - arch_name = (char *) arm_arch(arch); + arch_name = (char*) arm_arch(arch); if (imp_name || part_desc) { if (arch_name != arch) sprintf(dnbuff, "%s %s r%dp%d (%s)", |