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-rw-r--r--modules/devices/riscv/processor.c2
-rw-r--r--modules/devices/riscv/riscv_data.c9
2 files changed, 7 insertions, 4 deletions
diff --git a/modules/devices/riscv/processor.c b/modules/devices/riscv/processor.c
index d44ca542..cd8da4c7 100644
--- a/modules/devices/riscv/processor.c
+++ b/modules/devices/riscv/processor.c
@@ -104,7 +104,7 @@ processor_scan(void)
processor = (Processor *) pi->data;
/* strings can't be null or segfault later */
- STRIFNULL(processor->model_name, _("RISC-V Processor") );
+ STRIFNULL(processor->model_name, "RISC-V Processor" );
UNKIFNULL(processor->mmu);
UNKIFNULL(processor->isa);
UNKIFNULL(processor->uarch);
diff --git a/modules/devices/riscv/riscv_data.c b/modules/devices/riscv/riscv_data.c
index 917e8e06..526067d3 100644
--- a/modules/devices/riscv/riscv_data.c
+++ b/modules/devices/riscv/riscv_data.c
@@ -47,6 +47,9 @@ static struct {
{ "Q", NC_("rv-ext", /*/ext:Q*/ "Floating-point instructions, quad-precision") },
{ "B", NC_("rv-ext", /*/ext:B*/ "Bit manipulation instructions") },
{ "V", NC_("rv-ext", /*/ext:V*/ "Vector operations") },
+ { "Zk", NC_("rv-ext", /*/ext:Zk*/ "Scalar Cryptography") },
+ { "S", NC_("rv-ext", /*/ext:S*/ "Supervisor-level Instructions") },
+ { "U", NC_("rv-ext", /*/ext:U*/ "User Mode") },
{ "T", NC_("rv-ext", /*/ext:T*/ "Transactional memory") },
{ "P", NC_("rv-ext", /*/ext:P*/ "Packed SIMD instructions") },
{ "L", NC_("rv-ext", /*/ext:L*/ "Decimal floating-point instructions") },
@@ -139,10 +142,10 @@ static int riscv_isa_next(const char *isap, char *flag) {
}
switch(*p) {
- case 'S': case 's': /* supervisor extension */
- case 'X': case 'x': /* custom extension */
+ // case 'S': case 's': /* supervisor extension */
+ // case 'X': case 'x': /* custom extension */
/* custom supervisor extension (SX..) handled by S */
- break;
+ // break;
default: /* single character (standard) extension */
tag_len = 1;
if (next_digit != p+1) ver_len = 0;