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2024-03-09FIX Risc V Supervisor flag handlinghwspeedy
2024-03-09ADD Risc V new isa Zk,S,Uhwspeedy
2024-03-05FIX Risc-V cpu model was translatedhwspeedy
2024-02-24FIX RISC-V processor informationhwspeedy
2024-02-08LICENSE Changed to GPL2+ for project and source code According to approval ↵bigbear
from copyright holders - see: https://github.com/lpereira/hardinfo/issues/530 https://github.com/lpereira/hardinfo/issues/707
2021-11-07Update copyright informationL Pereira
2020-12-22docs: fix simple typo, insensitve -> insensitiveTim Gates
There is a small typo in modules/devices/riscv/riscv_data.c. Should read `insensitive` rather than `insensitve`.
2017-08-11Make MHz translatable in CPU listBurt P
It was kindof translatable before, but as part of a messy use-once c-format string. In this form it is re-usable elsewhere. Signed-off-by: Burt P <pburt0@gmail.com>
2017-08-11Separate processor name and description + count cores and threadsBurt P
* add cpu_procs_cores_threads() function to get counts from sysfs/topology * each platform must now provide processor_name() and processor_describe() * processor_name_default(): returns a list of unique processor->model_name * processor_describe_default(): returns "N physical; M cores; L threads" * processor_describe_by_counting_names(): returns a list of unique processor->model_name with Nx prefix (ex: "4x ARM Cortex A53 + 4x ARM Cortex A33") * x86: _name and _describe use defaults * arm: _name returns name of SOC, if available, _describe returns processor_describe_by_counting_names() * all other platforms: _name and _describe use defaults * Computer module summary now shows both name and description for CPU Signed-off-by: Burt P <pburt0@gmail.com>
2017-07-25device tree: fix crash when device tree is not foundBurt P
* check if device tree was found before add_keys() * UNKIFNULL(model) before strcmp * make UNKIFNULL() STRIFNULL() EMPIFNULL() macros more generic Signed-off-by: Burt P <pburt0@gmail.com>
2017-07-19x86,arm,riscv: Use gettext contexts and comments for cpu flagsBurt P
* flag defintion strings are grouped into contexts: x86-flag, arm-flag, riscv-ext * a comment is included for translators so that they know what flag the string defines without looking at the source code Signed-off-by: Burt P <pburt0@gmail.com>
2017-07-12x86,arm,riscv: small fixes and flag definition cosmetic tweaksBurt P
Signed-off-by: Burt P <pburt0@gmail.com>
2017-07-12x86,arm,riscv: make flag definitions translatableBurt P
Signed-off-by: Burt P <pburt0@gmail.com>
2017-07-12riscv: improve ISA string decodingBurt P
* Handle unknown future standard extensions better * Handle extension version numbers instead of just ignoring them * Test file riscv_fake_cpuinfo made more tricky Signed-off-by: Burt P <pburt0@gmail.com>
2017-07-12minor changesBurt P
Signed-off-by: Burt P <pburt0@gmail.com>
2017-07-12riscv: improvementsBurt P
Signed-off-by: Burt P <pburt0@gmail.com>
2017-07-12riscv: show extension setsBurt P
Signed-off-by: Burt P <pburt0@gmail.com>
2017-07-12riscv: initial supportBurt P
Signed-off-by: Burt P <pburt0@gmail.com>
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