From 2a0146b4312c4171828e8faf8438cf1cb9e6447b Mon Sep 17 00:00:00 2001
From: Burt P <pburt0@gmail.com>
Date: Mon, 10 Jul 2017 18:12:49 -0500
Subject: x86,arm,riscv: make flag definitions translatable

Signed-off-by: Burt P <pburt0@gmail.com>
---
 modules/devices/arm/arm_data.c | 83 +++++++++++++++++++++++-------------------
 1 file changed, 45 insertions(+), 38 deletions(-)

(limited to 'modules/devices/arm')

diff --git a/modules/devices/arm/arm_data.c b/modules/devices/arm/arm_data.c
index 2e2cbe60..a57e7b52 100644
--- a/modules/devices/arm/arm_data.c
+++ b/modules/devices/arm/arm_data.c
@@ -23,6 +23,13 @@
 #include <string.h>
 #include "arm_data.h"
 
+#ifndef _
+#define _(String) String
+#endif
+#ifndef N_
+#define N_(String) String
+#endif
+
 /* sources:
  *   https://unix.stackexchange.com/a/43563
  *   git:linux/arch/arm/kernel/setup.c
@@ -32,45 +39,45 @@ static struct {
     char *name, *meaning;
 } tab_flag_meaning[] = {
     /* arm/hw_cap */
-    { "swp",	"SWP instruction (atomic read-modify-write)" },
-    { "half",	"Half-word loads and stores" },
-    { "thumb",	"Thumb (16-bit instruction set)" },
-    { "26bit",	"26-Bit Model (Processor status register folded into program counter)" },
-    { "fastmult",	"32x32->64-bit multiplication" },
-    { "fpa",	"Floating point accelerator" },
-    { "vfp",	"VFP (early SIMD vector floating point instructions)" },
-    { "edsp",	"DSP extensions (the 'e' variant of the ARM9 CPUs, and all others above)" },
-    { "java",	"Jazelle (Java bytecode accelerator)" },
-    { "iwmmxt",	"SIMD instructions similar to Intel MMX" },
-    { "crunch",	"MaverickCrunch coprocessor (if kernel support enabled)" },
-    { "thumbee",	"ThumbEE" },
-    { "neon",	"Advanced SIMD/NEON on AArch32" },
-    { "evtstrm",	"kernel event stream using generic architected timer" },
-    { "vfpv3",	"VFP version 3" },
-    { "vfpv3d16",	"VFP version 3 with 16 D-registers" },
-    { "vfpv4",	"VFP version 4 with fast context switching" },
-    { "vfpd32",	"VFP with 32 D-registers" },
-    { "tls",	"TLS register" },
-    { "idiva",	"SDIV and UDIV hardware division in ARM mode" },
-    { "idivt",	"SDIV and UDIV hardware division in Thumb mode" },
-    { "lpae",	"40-bit Large Physical Address Extension" },
+    { "swp",	N_("SWP instruction (atomic read-modify-write)") },
+    { "half",	N_("Half-word loads and stores") },
+    { "thumb",	N_("Thumb (16-bit instruction set)") },
+    { "26bit",	N_("26-Bit Model (Processor status register folded into program counter)") },
+    { "fastmult",	N_("32x32->64-bit multiplication") },
+    { "fpa",	N_("Floating point accelerator") },
+    { "vfp",	N_("VFP (early SIMD vector floating point instructions)") },
+    { "edsp",	N_("DSP extensions (the 'e' variant of the ARM9 CPUs, and all others above)") },
+    { "java",	N_("Jazelle (Java bytecode accelerator)") },
+    { "iwmmxt",	N_("SIMD instructions similar to Intel MMX") },
+    { "crunch",	N_("MaverickCrunch coprocessor (if kernel support enabled)") },
+    { "thumbee",	N_("ThumbEE") },
+    { "neon",	N_("Advanced SIMD/NEON on AArch32") },
+    { "evtstrm",	N_("kernel event stream using generic architected timer") },
+    { "vfpv3",	N_("VFP version 3") },
+    { "vfpv3d16",	N_("VFP version 3 with 16 D-registers") },
+    { "vfpv4",	N_("VFP version 4 with fast context switching") },
+    { "vfpd32",	N_("VFP with 32 D-registers") },
+    { "tls",	N_("TLS register") },
+    { "idiva",	N_("SDIV and UDIV hardware division in ARM mode") },
+    { "idivt",	N_("SDIV and UDIV hardware division in Thumb mode") },
+    { "lpae",	N_("40-bit Large Physical Address Extension") },
     /* arm/hw_cap2 */
-    { "pmull",	"64x64->128-bit F2m multiplication (arch>8)" },
-    { "aes",	"Crypto:AES (arch>8)" },
-    { "sha1",	"Crypto:SHA1 (arch>8)" },
-    { "sha2",	"Crypto:SHA2 (arch>8)" },
-    { "crc32",	"CRC32 checksum instructions (arch>8)" },
+    { "pmull",	N_("64x64->128-bit F2m multiplication (arch>8)") },
+    { "aes",	N_("Crypto:AES (arch>8)") },
+    { "sha1",	N_("Crypto:SHA1 (arch>8)") },
+    { "sha2",	N_("Crypto:SHA2 (arch>8)") },
+    { "crc32",	N_("CRC32 checksum instructions (arch>8)") },
     /* arm64/hw_cap */
-    { "fp",	"" },
-    { "asimd",	"Advanced SIMD/NEON on AArch64 (arch>8)" },
-    { "atomics",	"" },
-    { "fphp",	"" },
-    { "asimdhp",	"" },
-    { "cpuid",	"" },
-    { "asimdrdm",	"" },
-    { "jscvt",	"" },
-    { "fcma",	"" },
-    { "lrcpc",	"" },
+    { "fp",	N_("") },
+    { "asimd",	N_("Advanced SIMD/NEON on AArch64 (arch>8)") },
+    { "atomics",	N_("") },
+    { "fphp",	N_("") },
+    { "asimdhp",	N_("") },
+    { "cpuid",	N_("") },
+    { "asimdrdm",	N_("") },
+    { "jscvt",	N_("") },
+    { "fcma",	N_("") },
+    { "lrcpc",	N_("") },
 
     { NULL, NULL},
 };
@@ -144,7 +151,7 @@ const char *arm_flag_meaning(const char *flag) {
     if (flag)
     while(tab_flag_meaning[i].name != NULL) {
         if (strcmp(tab_flag_meaning[i].name, flag) == 0)
-            return tab_flag_meaning[i].meaning;
+            return _(tab_flag_meaning[i].meaning);
         i++;
     }
     return NULL;
-- 
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