From 703651e21ce78d3cf575975310c959dffcacc5c4 Mon Sep 17 00:00:00 2001 From: hwspeedy Date: Sat, 9 Mar 2024 01:50:13 +0100 Subject: ADD Risc V new isa Zk,S,U --- modules/devices/riscv/riscv_data.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'modules/devices/riscv') diff --git a/modules/devices/riscv/riscv_data.c b/modules/devices/riscv/riscv_data.c index 917e8e06..fc6d939a 100644 --- a/modules/devices/riscv/riscv_data.c +++ b/modules/devices/riscv/riscv_data.c @@ -47,6 +47,9 @@ static struct { { "Q", NC_("rv-ext", /*/ext:Q*/ "Floating-point instructions, quad-precision") }, { "B", NC_("rv-ext", /*/ext:B*/ "Bit manipulation instructions") }, { "V", NC_("rv-ext", /*/ext:V*/ "Vector operations") }, + { "Zk", NC_("rv-ext", /*/ext:Zk*/ "Scalar Cryptography") }, + { "S", NC_("rv-ext", /*/ext:S*/ "Supervisor-level Instructions") }, + { "U", NC_("rv-ext", /*/ext:U*/ "User Mode") }, { "T", NC_("rv-ext", /*/ext:T*/ "Transactional memory") }, { "P", NC_("rv-ext", /*/ext:P*/ "Packed SIMD instructions") }, { "L", NC_("rv-ext", /*/ext:L*/ "Decimal floating-point instructions") }, -- cgit v1.2.3