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-rw-r--r--modules/devices/riscv/processor.c233
-rw-r--r--modules/devices/riscv/riscv_data.c212
-rw-r--r--modules/devices/riscv/riscv_data.h33
3 files changed, 478 insertions, 0 deletions
diff --git a/modules/devices/riscv/processor.c b/modules/devices/riscv/processor.c
new file mode 100644
index 00000000..f2e51c91
--- /dev/null
+++ b/modules/devices/riscv/processor.c
@@ -0,0 +1,233 @@
+/*
+ * HardInfo - Displays System Information
+ * Copyright (C) 2003-2006 L. A. F. Pereira <l@tia.mat.br>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 or later.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* source: https://github.com/riscv/riscv-linux/blob/riscv-next/arch/riscv/kernel/cpu.c */
+
+#include "hardinfo.h"
+#include "devices.h"
+#include "cpu_util.h"
+
+#include "riscv_data.h"
+#include "riscv_data.c"
+
+GSList *
+processor_scan(void)
+{
+ GSList *procs = NULL;
+ Processor *processor = NULL;
+ FILE *cpuinfo;
+ gchar buffer[128];
+ gchar *rep_pname = NULL;
+ gchar *tmpfreq_str = NULL;
+ GSList *pi = NULL;
+
+ cpuinfo = fopen(PROC_CPUINFO, "r");
+ if (!cpuinfo)
+ return NULL;
+
+#define CHECK_FOR(k) (g_str_has_prefix(tmp[0], k))
+ while (fgets(buffer, 128, cpuinfo)) {
+ gchar **tmp = g_strsplit(buffer, ":", 2);
+ if (tmp[0] && tmp[1]) {
+ tmp[0] = g_strstrip(tmp[0]);
+ tmp[1] = g_strstrip(tmp[1]);
+ } else {
+ g_strfreev(tmp);
+ continue;
+ }
+
+ //get_str("Processor", rep_pname);
+
+ if ( CHECK_FOR("hart") ) {
+ /* finish previous */
+ if (processor) {
+ procs = g_slist_append(procs, processor);
+ }
+
+ /* start next */
+ processor = g_new0(Processor, 1);
+ processor->id = atol(tmp[1]);
+
+ if (rep_pname)
+ processor->model_name = g_strdup(rep_pname);
+
+ g_strfreev(tmp);
+ continue;
+ }
+
+ if (!processor &&
+ ( CHECK_FOR("mmu")
+ || CHECK_FOR("isa")
+ || CHECK_FOR("uarch") ) ) {
+
+ /* single proc/core may not have "hart : n" */
+ processor = g_new0(Processor, 1);
+ processor->id = 0;
+
+ if (rep_pname)
+ processor->model_name = g_strdup(rep_pname);
+ }
+
+ if (processor) {
+ get_str("mmu", processor->mmu);
+ get_str("isa", processor->isa);
+ get_str("uarch", processor->uarch);
+ }
+ g_strfreev(tmp);
+ }
+
+ if (processor)
+ procs = g_slist_append(procs, processor);
+
+ g_free(rep_pname);
+ fclose(cpuinfo);
+
+ /* TODO: redup */
+
+ /* data not from /proc/cpuinfo */
+ for (pi = procs; pi; pi = pi->next) {
+ processor = (Processor *) pi->data;
+
+ /* strings can't be null or segfault later */
+ STRIFNULL(processor->model_name, _("RISC-V Processor") );
+ UNKIFNULL(processor->mmu);
+ UNKIFNULL(processor->isa);
+ UNKIFNULL(processor->uarch);
+
+ processor->flags = riscv_isa_to_flags(processor->isa);
+
+ /* topo & freq */
+ processor->cpufreq = cpufreq_new(processor->id);
+ processor->cputopo = cputopo_new(processor->id);
+
+ if (processor->cpufreq->cpukhz_max)
+ processor->cpu_mhz = processor->cpufreq->cpukhz_max / 1000;
+ else
+ processor->cpu_mhz = 0.0f;
+ }
+
+ return procs;
+}
+
+gchar *processor_get_capabilities_from_flags(gchar * strflags)
+{
+ gchar **flags, **old;
+ gchar *tmp = NULL;
+ gint j = 0;
+
+ flags = g_strsplit(strflags, " ", 0);
+ old = flags;
+
+ while (flags[j]) {
+ const gchar *meaning = riscv_ext_meaning( flags[j] );
+
+ if (meaning) {
+ tmp = h_strdup_cprintf("%s=%s\n", tmp, flags[j], meaning);
+ } else {
+ tmp = h_strdup_cprintf("%s=\n", tmp, flags[j]);
+ }
+ j++;
+ }
+ if (tmp == NULL || g_strcmp0(tmp, "") == 0)
+ tmp = g_strdup_printf("%s=%s\n", "empty", _("Empty List"));
+
+ g_strfreev(old);
+ return tmp;
+}
+
+gchar *processor_name(GSList * processors) {
+ return processor_name_default(processors);
+}
+
+gchar *processor_describe(GSList * processors) {
+ return processor_describe_default(processors);
+}
+
+gchar *
+processor_get_detailed_info(Processor *processor)
+{
+ gchar *tmp_flags, *tmp_cpufreq, *tmp_topology, *ret;
+ tmp_flags = processor_get_capabilities_from_flags(processor->flags);
+ tmp_topology = cputopo_section_str(processor->cputopo);
+ tmp_cpufreq = cpufreq_section_str(processor->cpufreq);
+
+ ret = g_strdup_printf("[%s]\n"
+ "%s=%s\n" /* model */
+ "%s=%s\n" /* isa */
+ "%s=%s\n" /* uarch */
+ "%s=%s\n" /* mmu */
+ "%s=%.2f %s\n" /* frequency */
+ "%s=%s\n" /* byte order */
+ "%s" /* topology */
+ "%s" /* frequency scaling */
+ "[%s]\n" /* extensions */
+ "%s"
+ "%s",/* empty */
+ _("Processor"),
+ _("Model"), processor->model_name,
+ _("Architecture"), processor->isa,
+ _("uarch"), processor->uarch,
+ _("MMU"), processor->mmu,
+ _("Frequency"), processor->cpu_mhz, _("MHz"),
+ _("Byte Order"), byte_order_str(),
+ tmp_topology,
+ tmp_cpufreq,
+ _("Capabilities"), tmp_flags,
+ "");
+ g_free(tmp_flags);
+ g_free(tmp_cpufreq);
+ g_free(tmp_topology);
+ return ret;
+}
+
+gchar *processor_get_info(GSList * processors)
+{
+ Processor *processor;
+
+ if (g_slist_length(processors) > 1) {
+ gchar *ret, *tmp, *hashkey;
+ GSList *l;
+
+ tmp = g_strdup("");
+
+ for (l = processors; l; l = l->next) {
+ processor = (Processor *) l->data;
+
+ tmp = g_strdup_printf("%s$CPU%d$%s=%.2f %s\n",
+ tmp, processor->id,
+ processor->model_name,
+ processor->cpu_mhz, _("MHz"));
+
+ hashkey = g_strdup_printf("CPU%d", processor->id);
+ moreinfo_add_with_prefix("DEV", hashkey,
+ processor_get_detailed_info(processor));
+ g_free(hashkey);
+ }
+
+ ret = g_strdup_printf("[$ShellParam$]\n"
+ "ViewType=1\n"
+ "[Processors]\n"
+ "%s", tmp);
+ g_free(tmp);
+
+ return ret;
+ }
+
+ processor = (Processor *) processors->data;
+ return processor_get_detailed_info(processor);
+}
diff --git a/modules/devices/riscv/riscv_data.c b/modules/devices/riscv/riscv_data.c
new file mode 100644
index 00000000..917e8e06
--- /dev/null
+++ b/modules/devices/riscv/riscv_data.c
@@ -0,0 +1,212 @@
+/*
+ * rpiz - https://github.com/bp0/rpiz
+ * Copyright (C) 2017 Burt P. <pburt0@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <ctype.h>
+#include "riscv_data.h"
+
+#ifndef C_
+#define C_(Ctx, String) String
+#endif
+#ifndef NC_
+#define NC_(Ctx, String) String
+#endif
+
+static struct {
+ char *name, *meaning;
+} tab_ext_meaning[] = {
+ { "RV32", NC_("rv-ext", /*/ext:RV32*/ "RISC-V 32-bit") },
+ { "RV64", NC_("rv-ext", /*/ext:RV64*/ "RISC-V 64-bit") },
+ { "RV128", NC_("rv-ext", /*/ext:RV128*/ "RISC-V 128-bit") },
+ { "E", NC_("rv-ext", /*/ext:E*/ "Base embedded integer instructions (15 registers)") },
+ { "I", NC_("rv-ext", /*/ext:I*/ "Base integer instructions (31 registers)") },
+ { "M", NC_("rv-ext", /*/ext:M*/ "Hardware integer multiply and divide") },
+ { "A", NC_("rv-ext", /*/ext:A*/ "Atomic memory operations") },
+ { "C", NC_("rv-ext", /*/ext:C*/ "Compressed 16-bit instructions") },
+ { "F", NC_("rv-ext", /*/ext:F*/ "Floating-point instructions, single-precision") },
+ { "D", NC_("rv-ext", /*/ext:D*/ "Floating-point instructions, double-precision") },
+ { "Q", NC_("rv-ext", /*/ext:Q*/ "Floating-point instructions, quad-precision") },
+ { "B", NC_("rv-ext", /*/ext:B*/ "Bit manipulation instructions") },
+ { "V", NC_("rv-ext", /*/ext:V*/ "Vector operations") },
+ { "T", NC_("rv-ext", /*/ext:T*/ "Transactional memory") },
+ { "P", NC_("rv-ext", /*/ext:P*/ "Packed SIMD instructions") },
+ { "L", NC_("rv-ext", /*/ext:L*/ "Decimal floating-point instructions") },
+ { "J", NC_("rv-ext", /*/ext:J*/ "Dynamically translated languages") },
+ { "N", NC_("rv-ext", /*/ext:N*/ "User-level interrupts") },
+ { NULL, NULL }
+};
+
+static char all_extensions[1024] = "";
+
+#define APPEND_EXT(f) strcat(all_extensions, f); strcat(all_extensions, " ");
+const char *riscv_ext_list() {
+ int i = 0, built = 0;
+ built = strlen(all_extensions);
+ if (!built) {
+ while(tab_ext_meaning[i].name != NULL) {
+ APPEND_EXT(tab_ext_meaning[i].name);
+ i++;
+ }
+ }
+ return all_extensions;
+}
+
+const char *riscv_ext_meaning(const char *ext) {
+ int i = 0, l = 0;
+ char *c = NULL;
+ if (ext) {
+ c = strchr(ext, ':'); /* allow extension:version, ignore version */
+ if (c != NULL)
+ l = c - ext;
+ else
+ l = strlen(ext);
+ while(tab_ext_meaning[i].name != NULL) {
+ if (strncasecmp(tab_ext_meaning[i].name, ext, l) == 0) {
+ if (tab_ext_meaning[i].meaning != NULL)
+ return C_("rv-ext", tab_ext_meaning[i].meaning);
+ else return NULL;
+ }
+ i++;
+ }
+ }
+ return NULL;
+}
+
+/* see RISC-V spec 2.2: Chapter 22: ISA Subset Naming Conventions */
+
+/* Spec says case-insensitive, but I prefer single-letter extensions
+ * capped and version string (like "2p1") with a lowercase p. */
+#define RV_FIX_CASE(fstr,vo) \
+ p = fstr; while (*p != 0 && *p != ':') { if (!vo) *p = toupper(*p); p++; } \
+ if (*p == ':') while (*p != 0) { if (*p == 'P') *p = 'p'; p++; }
+
+static int riscv_isa_next(const char *isap, char *flag) {
+ char *p = NULL, *start = NULL;
+ char *next_sep = NULL, *next_digit = NULL;
+ int skip_len = 0, tag_len = 0, ver_len = 0;
+ char ext_str[32], ver_str[32];
+
+ if (isap == NULL)
+ return 0;
+
+ /* find start by skipping any '_' */
+ start = (char*)isap;
+ while (*start != 0 && *start == '_') { start++; skip_len++; };
+ if (*start == 0)
+ return 0;
+
+ /* find next '_' or \0 */
+ p = start; while (*p != 0 && *p != '_') { p++; }; next_sep = p;
+
+ /* find next digit that may be a version, find length of version */
+ p = start; while (*p != 0 && !isdigit(*p)) { p++; };
+ if (isdigit(*p)) next_digit = p;
+ if (next_digit) {
+ while (*p != 0 && (isdigit(*p) || *p == 'p' || *p == 'P') ) {
+ if ((*p == 'p' || *p == 'P') && !isdigit(*(p+1)) )
+ break;
+ ver_len++;
+ p++;
+ }
+ }
+
+ /* is next version nearer than next separator */
+ p = start;
+ if (next_digit && next_digit < next_sep)
+ tag_len = next_digit - p;
+ else {
+ tag_len = next_sep - p;
+ ver_len = 0;
+ }
+
+ switch(*p) {
+ case 'S': case 's': /* supervisor extension */
+ case 'X': case 'x': /* custom extension */
+ /* custom supervisor extension (SX..) handled by S */
+ break;
+ default: /* single character (standard) extension */
+ tag_len = 1;
+ if (next_digit != p+1) ver_len = 0;
+ break;
+ }
+
+ memset(ext_str, 0, 32);
+ memset(ver_str, 0, 32);
+ if (ver_len) {
+ strncpy(ext_str, p, tag_len);
+ strncpy(ver_str, next_digit, ver_len);
+ sprintf(flag, "%s:%s", ext_str, ver_str);
+ if (tag_len == 1) {
+ RV_FIX_CASE(flag, 0);
+ } else {
+ RV_FIX_CASE(flag, 1);
+ }
+ return skip_len + tag_len + ver_len;
+ } else {
+ strncpy(ext_str, p, tag_len);
+ sprintf(flag, "%s", ext_str);
+ if (tag_len == 1) { RV_FIX_CASE(flag, 0); }
+ return skip_len + tag_len;
+ }
+}
+
+#define FSTR_SIZE 1024
+#define RV_CHECK_FOR(e) ( strncasecmp(ps, e, 2) == 0 )
+#define ADD_EXT_FLAG(ext) el = strlen(ext); strncpy(pd, ext, el); strncpy(pd + el, " ", 1); pd += el + 1;
+char *riscv_isa_to_flags(const char *isa) {
+ char *flags = NULL, *ps = (char*)isa, *pd = NULL;
+ char flag_buf[64] = "";
+ int isa_len = 0, tl = 0, el = 0; /* el used in macro */
+
+ if (isa) {
+ isa_len = strlen(isa);
+ flags = malloc(FSTR_SIZE);
+ if (flags) {
+ memset(flags, 0, FSTR_SIZE);
+ ps = (char*)isa;
+ pd = flags;
+ if ( RV_CHECK_FOR("RV") )
+ { ps += 2; }
+ if ( RV_CHECK_FOR("32") )
+ { ADD_EXT_FLAG("RV32"); ps += 2; }
+ else if ( RV_CHECK_FOR("64") )
+ { ADD_EXT_FLAG("RV64"); ps += 2; }
+ else if ( RV_CHECK_FOR("128") )
+ { ADD_EXT_FLAG("RV128"); ps += 3; }
+
+ while( (tl = riscv_isa_next(ps, flag_buf)) ) {
+ if (flag_buf[0] == 'G') { /* G = IMAFD */
+ flag_buf[0] = 'I'; ADD_EXT_FLAG(flag_buf);
+ flag_buf[0] = 'M'; ADD_EXT_FLAG(flag_buf);
+ flag_buf[0] = 'A'; ADD_EXT_FLAG(flag_buf);
+ flag_buf[0] = 'F'; ADD_EXT_FLAG(flag_buf);
+ flag_buf[0] = 'D'; ADD_EXT_FLAG(flag_buf);
+ } else {
+ ADD_EXT_FLAG(flag_buf);
+ }
+ ps += tl;
+ if (ps - isa >= isa_len) break; /* just in case */
+ }
+ }
+ }
+ return flags;
+}
diff --git a/modules/devices/riscv/riscv_data.h b/modules/devices/riscv/riscv_data.h
new file mode 100644
index 00000000..1d3a0a48
--- /dev/null
+++ b/modules/devices/riscv/riscv_data.h
@@ -0,0 +1,33 @@
+/*
+ * rpiz - https://github.com/bp0/rpiz
+ * Copyright (C) 2017 Burt P. <pburt0@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+
+#ifndef _RISCVDATA_H_
+#define _RISCVDATA_H_
+
+/* convert RISC-V ISA string to flags list */
+char *riscv_isa_to_flags(const char *isa);
+
+/* all known extensions as flags list */
+const char *riscv_ext_list(void);
+
+/* get meaning of flag */
+const char *riscv_ext_meaning(const char *ext);
+
+#endif
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