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Age	Commit message (Collapse)	Author
2024-03-09	FIX Risc V Supervisor flag handling	hwspeedy

2024-03-09	ADD Risc V new isa Zk,S,U	hwspeedy

2020-12-22	docs: fix simple typo, insensitve -> insensitive	Tim Gates
	There is a small typo in modules/devices/riscv/riscv_data.c. Should read `insensitive` rather than `insensitve`.
2017-07-19	x86,arm,riscv: Use gettext contexts and comments for cpu flags	Burt P
	* flag defintion strings are grouped into contexts: x86-flag, arm-flag, riscv-ext * a comment is included for translators so that they know what flag the string defines without looking at the source code Signed-off-by: Burt P <pburt0@gmail.com>
2017-07-12	x86,arm,riscv: small fixes and flag definition cosmetic tweaks	Burt P
	Signed-off-by: Burt P <pburt0@gmail.com>
2017-07-12	x86,arm,riscv: make flag definitions translatable	Burt P
	Signed-off-by: Burt P <pburt0@gmail.com>
2017-07-12	riscv: improve ISA string decoding	Burt P
	* Handle unknown future standard extensions better * Handle extension version numbers instead of just ignoring them * Test file riscv_fake_cpuinfo made more tricky Signed-off-by: Burt P <pburt0@gmail.com>
2017-07-12	riscv: improvements	Burt P
	Signed-off-by: Burt P <pburt0@gmail.com>
2017-07-12	riscv: show extension sets	Burt P
	Signed-off-by: Burt P <pburt0@gmail.com>