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riscv
Age
Commit message (
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Author
2024-05-24
FIX GCC warnings arch/GCC version related
hwspeedy
2024-03-09
FIX Risc V Supervisor flag handling
hwspeedy
2024-03-09
ADD Risc V new isa Zk,S,U
hwspeedy
2024-03-05
FIX Risc-V cpu model was translated
hwspeedy
2024-02-24
FIX RISC-V processor information
hwspeedy
2024-02-08
LICENSE Changed to GPL2+ for project and source code According to approval fr...
bigbear
2021-11-07
Update copyright information
L Pereira
2020-12-22
docs: fix simple typo, insensitve -> insensitive
Tim Gates
2017-08-11
Make MHz translatable in CPU list
Burt P
2017-08-11
Separate processor name and description + count cores and threads
Burt P
2017-07-25
device tree: fix crash when device tree is not found
Burt P
2017-07-19
x86,arm,riscv: Use gettext contexts and comments for cpu flags
Burt P
2017-07-12
x86,arm,riscv: small fixes and flag definition cosmetic tweaks
Burt P
2017-07-12
x86,arm,riscv: make flag definitions translatable
Burt P
2017-07-12
riscv: improve ISA string decoding
Burt P
2017-07-12
minor changes
Burt P
2017-07-12
riscv: improvements
Burt P
2017-07-12
riscv: show extension sets
Burt P
2017-07-12
riscv: initial support
Burt P