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AgeCommit message (Expand)Author
2024-05-24FIX GCC warnings arch/GCC version relatedhwspeedy
2024-03-09FIX Risc V Supervisor flag handlinghwspeedy
2024-03-09ADD Risc V new isa Zk,S,Uhwspeedy
2024-03-05FIX Risc-V cpu model was translatedhwspeedy
2024-02-24FIX RISC-V processor informationhwspeedy
2024-02-08LICENSE Changed to GPL2+ for project and source code According to approval fr...bigbear
2021-11-07Update copyright informationL Pereira
2020-12-22docs: fix simple typo, insensitve -> insensitiveTim Gates
2017-08-11Make MHz translatable in CPU listBurt P
2017-08-11Separate processor name and description + count cores and threadsBurt P
2017-07-25device tree: fix crash when device tree is not foundBurt P
2017-07-19x86,arm,riscv: Use gettext contexts and comments for cpu flagsBurt P
2017-07-12x86,arm,riscv: small fixes and flag definition cosmetic tweaksBurt P
2017-07-12x86,arm,riscv: make flag definitions translatableBurt P
2017-07-12riscv: improve ISA string decodingBurt P
2017-07-12minor changesBurt P
2017-07-12riscv: improvementsBurt P
2017-07-12riscv: show extension setsBurt P
2017-07-12riscv: initial supportBurt P