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path: root/drivers/clk
AgeCommit message (Expand)Author
2019-02-11clk: s2mps11: Add used attribute to s2mps11_dt_matchNathan Chancellor
2019-02-11clk: s2mps11: Fix matching when built as module and DT node contains compatibleKrzysztof Kozlowski
2018-11-20clk: si5351: Constify clock names and struct regmap_configKrzysztof Kozlowski
2018-11-20clk: qcom: Base rcg parent rate off plan frequencyEvan Green
2018-02-13clk: ti: dra7-atl-clock: fix child-node lookupsJohan Hovold
2018-02-13clk: ti: dra7-atl-clock: Fix of_node reference countingPeter Ujfalusi
2018-02-13clk: tegra: Fix cclk_lp divisor registerMichał Mirosław
2017-11-11clk/efm32gg: fix dt init prototypeUwe Kleine-König
2017-06-05clk: renesas: mstp: ensure register writes completeChris Brandt
2017-06-05clk: samsung: mark s3c...._clk_sleep_init() as __initMartin Kaiser
2017-06-05clk: hisilicon: fix lock assignmentLeo Yan
2017-06-05clk: wm831x: fix usleep_range with bad rangeNicholas Mc Guire
2017-03-16clk: renesas: mstp: Support 8-bit registers for r7s72100Chris Brandt
2017-03-16clk: clk-wm831x: fix a logic errorPan Bian
2017-02-23clk: divider: Fix clk_divider_round_rate() to use clk_readl()Geert Uytterhoeven
2016-05-01clk: xgene: Add missing parenthesis when clearing divider valueLoc Ho
2016-05-01clk: versatile: sp810: support reentranceLinus Walleij
2016-02-02clk: st: avoid uninitialized variable useArnd Bergmann
2016-02-02clk: xgene: Fix divider with non-zero shift valueLoc Ho
2015-12-13clk: versatile-icst: fix memory leakLinus Walleij
2015-10-30clk: ti: fix dual-registration of uart4_ickBen Dooks
2015-09-30clk: versatile: off by one in clk_sp810_timerclken_of_get()Dan Carpenter
2015-09-28clk: exynos4: Fix wrong clock for Exynos4x12 ADCKrzysztof Kozlowski
2015-07-15clk: ti: dra7-atl-clock: Fix possible ERR_PTR dereferenceKrzysztof Kozlowski
2015-07-15clk: Fix JSON output in debugfsStefan Wahren
2015-05-06clk: qcom: fix RCG M/N counter configurationArchit Taneja
2015-05-06clk: at91: usb: fix at91sam9x5 recalc, round and set rateBoris Brezillon
2015-05-06clk: tegra: Register the proper number of resetsThierry Reding
2015-03-23clk: divider: fix selection of divider when rounding to closestUwe Kleine-König
2015-03-23clk: divider: fix calculation of maximal parent rate for a given dividerUwe Kleine-König
2015-03-03sunxi: clk: Set sun6i-pll1 n_start = 1Hans de Goede
2015-03-03clk: sunxi: Support factor clocks with N factor starting not from 0Chen-Yu Tsai
2015-03-02clk-gate: fix bit # check in clk_register_gate()Sergei Shtylyov
2015-02-24clk: zynq: Force CPU_2X clock to be ungatedSoren Brinkmann
2015-01-22clk: Don't try to use a struct clk* after it could have been freedTomeu Vizoso
2015-01-22clk: berlin: bg2q: remove non-exist "smemc" gate clockJisheng Zhang
2015-01-22clk: at91: keep slow clk enabled to prevent system hangBoris Brezillon
2015-01-15clk: samsung: Fix double add of syscore ops after driver rebindKrzysztof Kozlowski
2014-12-10clk-divider: Fix READ_ONLY when divider > 1James Hogan
2014-10-05clk: qcom: Fix PLL rate configurationsStephen Boyd
2014-10-05clk: qcom: mdp_lut_clk is a child of mdp_srcStephen Boyd
2014-10-05clk: qcom: Fix MN frequency tables, parent map, and jpegdStephen Boyd
2014-10-05clk: ti: divider: Provide error check for incoming parameters in set_rateNishanth Menon
2014-10-05clk: prevent erronous parsing of children during rate changeTero Kristo
2014-10-05clk: ti: dra7-atl: Provide error check for incoming parameters in set_rateNishanth Menon
2014-07-31clk: ti: clk-7xx: Correct ABE DPLL configurationPeter Ujfalusi
2014-07-13Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette...Linus Torvalds
2014-07-13clk: spear3xx: Set proper clock parent of uart1/2Thomas Gleixner
2014-07-13clk: spear3xx: Use proper control register offsetThomas Gleixner
2014-07-11clk: exynos5420: Add IDs for clocks used in PD mfcArun Kumar K
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