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Age	Commit message (Expand)	Author
2021-08-12	clk: fix leak on devm_clk_bulk_get_all() unwind	Brian Norris
2021-08-12	clk: tegra: Implement disable_unused() of tegra_clk_sdmmc_mux_ops	Dmitry Osipenko
2021-08-12	clk: stm32f4: fix post divisor setup for I2S/SAI PLLs	Dario Binacchi
2021-07-19	clk: tegra: Ensure that PLLU configuration is applied properly	Dmitry Osipenko
2021-07-19	clk: tegra: Fix refcounting of gate clocks	Dmitry Osipenko
2021-07-19	clk: renesas: r8a77995: Add ZA2 clock	Kuninori Morimoto
2021-07-19	clk: renesas: rcar-usb2-clock-sel: Fix error handling in .probe()	Dinghao Liu
2021-07-14	clk: si5341: Update initialization magic	Robert Hancock
2021-07-14	clk: si5341: Check for input clock presence and PLL lock on startup	Robert Hancock
2021-07-14	clk: si5341: Avoid divide errors due to bogus register contents	Robert Hancock
2021-07-14	clk: si5341: Wait for DEVICE_READY on startup	Robert Hancock
2021-07-14	clk: qcom: clk-alpha-pll: fix CAL_L write in alpha_pll_fabia_prepare	Jonathan Marek
2021-07-14	clk: actions: Fix AHPPREDIV-H-AHB clock chain on Owl S500 SoC	Cristian Ciocaltea
2021-07-14	clk: actions: Fix bisp_factor_table based clocks on Owl S500 SoC	Cristian Ciocaltea
2021-07-14	clk: actions: Fix SD clocks factor table on Owl S500 SoC	Cristian Ciocaltea
2021-07-14	clk: actions: Fix UART clock dividers on Owl S500 SoC	Cristian Ciocaltea
2021-07-14	clk: imx8mq: remove SYS PLL 1/2 clock gates	Lucas Stach
2021-07-14	clk: vc5: fix output disabling when enabling a FOD	Luca Ceresoli
2021-07-14	clk: tegra30: Use 300MHz for video decoder by default	Dmitry Osipenko
2021-07-14	clk: meson: g12a: fix gp0 and hifi ranges	Jerome Brunet
2021-07-14	clk: agilex/stratix10: fix bypass representation	Dinh Nguyen
2021-07-14	clk: agilex/stratix10: remove noc_clk	Dinh Nguyen
2021-07-14	clk: agilex/stratix10/n5x: fix how the bypass_reg is handled	Dinh Nguyen
2021-05-19	clk: exynos7: Mark aclk_fsys1_200 as critical	Paweł Chmiel
2021-05-14	clk: uniphier: Fix potential infinite loop	Colin Ian King
2021-05-14	clk: qcom: apss-ipq-pll: Add missing MODULE_DEVICE_TABLE	Chen Hui
2021-05-14	clk: qcom: a53-pll: Add missing MODULE_DEVICE_TABLE	Chen Hui
2021-05-14	clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enable	Quanyang Wang
2021-05-14	clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callback	Quanyang Wang
2021-05-14	clk: imx: Fix reparenting of UARTs not associated with stdout	Adam Ford
2021-05-14	media: aspeed: fix clock handling logic	Jae Hyun Yoo
2021-05-14	clk: mvebu: armada-37xx-periph: Fix workaround for switching from L1 to L0	Pali Rohár
2021-05-14	clk: mvebu: armada-37xx-periph: Fix switching CPU freq from 250 Mhz to 1 GHz	Pali Rohár
2021-05-14	clk: mvebu: armada-37xx-periph: remove .set_parent method for CPU PM clock	Marek Behún
2021-05-11	clk: socfpga: arria10: Fix memory leak of socfpga_clk on error return	Colin Ian King
2021-04-14	clk: socfpga: fix iomem pointer cast on 64-bit	Krzysztof Kozlowski
2021-04-14	clk: fix invalid usage of list cursor in unregister	Lukasz Bartosik
2021-04-14	clk: fix invalid usage of list cursor in register	Lukasz Bartosik
2021-03-30	clk: qcom: gcc-sc7180: Use floor ops for the correct sdcc1 clk	Douglas Anderson
2021-03-17	clk: qcom: gpucc-msm8998: Add resets, cxc, fix flags on gpu_gx_gdsc	AngeloGioacchino Del Regno
2021-03-17	clk: qcom: gdsc: Implement NO_RET_PERIPH flag	AngeloGioacchino Del Regno
2021-03-04	clk: aspeed: Fix APLL calculate formula from ast2600-A2	Ryan Chen
2021-03-04	clk: divider: fix initialization with parent_hw	Michael Tretter
2021-03-04	clk: qcom: gcc-msm8998: Fix Alpha PLL type for all GPLLs	AngeloGioacchino Del Regno
2021-03-04	clk: sunxi-ng: h6: Fix clock divider range on some clocks	Andre Przywara
2021-03-04	clk: renesas: r8a779a0: Fix parent of CBFUSA clock	Geert Uytterhoeven
2021-03-04	clk: renesas: r8a779a0: Remove non-existent S2 clock	Geert Uytterhoeven
2021-03-04	clk: sunxi-ng: h6: Fix CEC clock	Andre Przywara
2021-03-04	clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate()	Martin Blumenstingl
2021-03-04	clk: meson: clk-pll: make "ret" a signed integer	Martin Blumenstingl